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Register at offset 0x404 is "Host Frame Interval Register" while in AS3525 datasheet and AMD5536UDC it is DEV_CTL (and I couldn't find at least one register that matches)
Here are some differences between the registers list in AS3525 datasheet and AMD5536UDC (perhaps different hardware revisions of the same chip?):
EP In Status Mask Register (EP in base + 0x18) is absent from AMD5536UDC datasheet
EP In Write Confirmation Register (EP in base + 0x1C) is absent from AS3525 datasheet
The RX & TX FIFOs are absent from both datasheets but are documented to be at 0x800 (RX) and 0xC00 (TX) in the linux driver source code.
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Anyone will be able to find and view this paste. Google will index it.
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