Thank you to anyone who has already donated - your generous donations helped make three months of treatment possible.
My brother Nate continues to fight stage IV Hodgkin's lymphoma. He's just 31, with a wife and baby girl. They have no active income (since he's been unable to return to work), no insurance, and cannot afford the treatment he needs. Nate and his family need your help. Please consider a donation, every dollar helps. Thanks.
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diff --git a/firmware/export/config.h b/firmware/export/config.h index e678590..9d8dc41 100644 Lyre prototype 1 */ #endif /* HAVE_USBSTACK */ -/* Storage alignment: the mask specifies a mask of bits which should be - * clear in addresses used for storage_{read,write}_sectors(). This is - * only relevant for buffers that will contain one or more whole sectors. - */ - -/* PP502x DMA requires an alignment of at least 16 bytes */ -#ifdef HAVE_ATA_DMA -#ifdef CPU_PP502x -#define STORAGE_ALIGN_MASK 15 -#endif -#endif /* HAVE_ATA_DMA */ - -/* by default no alignment is required */ -#ifndef STORAGE_ALIGN_MASK -#define STORAGE_ALIGN_MASK 0 -#endif - /* This attribute can be used to enable to detection of plugin file handles leaks. * When enabled, the plugin core will monitor open/close/creat and when the plugin exits * will display an error message if the plugin leaked some file handles */ diff --git a/firmware/export/config/ipodnano2g.h b/firmware/export/config/ipodnano2g.h index 0b69041..989d563 100644 //#define IPOD_ACCESSORY_PROTOCOL //#define HAVE_SERIAL -#define STORAGE_ALIGN_MASK 15 #define USB_WRITE_BUFFER_SIZE (1024*64) diff --git a/firmware/export/system.h b/firmware/export/system.h index 505b167..c4c762a 100644 static inline void cpucache_flush(void) #define CACHEALIGN_BUFFER(start, size) \ ALIGN_BUFFER((start), (size), CACHEALIGN_SIZE) +#ifdef NEEDS_STORAGE_ALIGN +#define STORAGE_ALIGN_MASK (CACHEALIGN_SIZE - 1) +#else +#define STORAGE_ALIGN_MASK 0 +#endif + #else /* ndef PROC_NEEDS_CACHEALIGN */ /* Cache alignment attributes and sizes are not enabled */ static inline void cpucache_flush(void) #define CACHEALIGN_DOWN(x) (x) /* Make no adjustments */ #define CACHEALIGN_BUFFER(start, size) +#define STORAGE_ALIGN_MASK 0 #endif /* PROC_NEEDS_CACHEALIGN */ diff --git a/firmware/target/arm/s5l8700/system-target.h b/firmware/target/arm/s5l8700/system-target.h index 81e5c7f..c531344 100644 #define CPUFREQ_NORMAL 47923200 #define CPUFREQ_MAX 191692800 +/* DMA engine needs aligned addresses */ +#define PROC_NEEDS_CACHEALIGN +#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ +#define NEEDS_STORAGE_ALIGN + #define inl(a) (*(volatile unsigned long *) (a)) #define outl(a,b) (*(volatile unsigned long *) (b) = (a)) #define inb(a) (*(volatile unsigned char *) (a)) diff --git a/firmware/target/arm/system-target.h b/firmware/target/arm/system-target.h index 764cd18..1422e64 100644 #ifndef SYSTEM_TARGET_H #define SYSTEM_TARGET_H +#include "config.h" #include "system-arm.h" #ifdef CPU_PP static inline void wake_core(int core) #define PROC_NEEDS_CACHEALIGN #define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */ +#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA) +#define NEEDS_STORAGE_ALIGN +#endif + /** cache functions **/ #ifndef BOOTLOADER #define HAVE_CPUCACHE_INVALIDATE |
