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diff --git a/firmware/target/arm/as3525/app.lds b/firmware/target/arm/as3525/app.lds
index c2fce0d..d6ea4c7 100644
--- a/firmware/target/arm/as3525/app.lds
+++ b/firmware/target/arm/as3525/app.lds
@@ -26,6 +26,7 @@ STARTUP(target/arm/crt0.o)
 #define IRAMSIZE (0x20000)
 #endif
 
+#define DRAM_RO_OFFSET (DRAM_SIZE + 0x100000)
 
 /* Where the codec buffer ends, and the plugin buffer starts */
 #if CODEC_BUFFER_FILLS_IRAM
@@ -46,14 +47,15 @@ MEMORY
 SECTIONS
 {
     loadaddress = DRAM_ORIG;
+    . = DRAM_ORIG;
 
-    .vectors :
+    .vectors . + DRAM_RO_OFFSET:
     {
         _vectors_start = .;
         *(.init.text)
-    } > DRAM
+    } AT> DRAM
 
-    .text :
+    .text . :
     {
         _loadaddress = .;
         _textstart = .;
@@ -61,13 +63,13 @@ SECTIONS
         *(.glue_7)
         *(.glue_7t)
         . = ALIGN(0x4);
-    } > DRAM
+    } AT> DRAM
 
-    .rodata :
+    .rodata . :
     {
         *(.rodata*)
         . = ALIGN(0x4);
-    } > DRAM
+    } AT> DRAM
 
     .data :
     {
diff --git a/firmware/target/arm/as3525/memory-init.S b/firmware/target/arm/as3525/memory-init.S
index 49b0546..2768a0d 100644
--- a/firmware/target/arm/as3525/memory-init.S
+++ b/firmware/target/arm/as3525/memory-init.S
@@ -147,6 +147,14 @@ memory_init:
     bl      map_section
 
     mov     r0, #0x30000000                 @ physical address
+    mov     r1, #DRAM_ORIG                  @ virtual address
+    add     r1, r1, #((MEMORYSIZE+1) * 0x100000)
+    mov     r2, #MEMORYSIZE                 @ size
+    mov     r3, #(1 << 3)           @ cacheable
+    add     r3, #(1 << 5)           @ domain 1 (Client)
+    bl      map_section
+
+    mov     r0, #0x30000000                 @ physical address
     mov     r1, #UNCACHED_ADDR(DRAM_ORIG)   @ virtual address
     mov     r2, #MEMORYSIZE                 @ size
     mov     r3, #CACHE_NONE
diff --git a/firmware/target/arm/mmu-arm.S b/firmware/target/arm/mmu-arm.S
index 522aa9f..84f8af1 100644
--- a/firmware/target/arm/mmu-arm.S
+++ b/firmware/target/arm/mmu-arm.S
@@ -93,6 +93,7 @@ ttb_init:
     ldr     r0, =TTB_BASE_ADDR      @
     mvn     r1, #0                  @
     mcr     p15, 0, r0, c2, c0, 0   @ Set the TTB base address
+    bic     r1, r1, #(1 << 3)       @ D1 = Client (access are checked)
     mcr     p15, 0, r1, c3, c0, 0   @ Set all domains to manager status
     bx      lr                      @
     .size   ttb_init, .-ttb_init
@@ -160,6 +161,7 @@ enable_mmu:
     orr     r0, r0, #1              @ enable mmu bit, i and dcache
     orr     r0, r0, #1<<2           @ enable dcache
     orr     r0, r0, #1<<12          @ enable icache
+    orr     r0, r0, #1<<9           @ ROM protection (read-only)
     mcr     p15, 0, r0, c1, c0, 0   @
     nop                             @
     nop                             @