Thank you to anyone who has already donated - your generous donations helped make three months of treatment possible.
My brother Nate continues to fight stage IV Hodgkin's lymphoma. He's just 31, with a wife and baby girl. They have no active income (since he's been unable to return to work), no insurance, and cannot afford the treatment he needs. Nate and his family need your help. Please consider a donation, every dollar helps. Thanks.
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static const ; static const ; static void { int i; for { data->core->OUTEP_REGS[i].DOEPINT = data->core->OUTEP_REGS[i].DOEPINT; data->core->INEP_REGS[i].DIEPINT = data->core->INEP_REGS[i].DIEPINT; } data->core->GREGS.GINTSTS = data->core->GREGS.GINTSTS; } void { // Find the appropriate set of endpoint registers volatile USB_OTG_OUTEPREGS* regs = &data->core->OUTEP_REGS[ep.number]; // Calculate number of packets (if size == 0 an empty packet will be sent) int maxpacket = regs->DOEPCTL.b.mps; int packets = (size + maxpacket - 1) / maxpacket; if (!packets) packets = 1; // Set up data desination if (data->use_dma) regs->DOEPDMA = buf; else data->state->endpoints[ep.number].rxaddr = (u32*)buf; USB_OTG_DEPXFRSIZ_TypeDef deptsiz = { .b = { .pktcnt = packets, .xfersize = size } }; regs->DOEPTSIZ = deptsiz; // Enable the endpoint USB_OTG_DEPCTL_TypeDef depctl = regs->DOEPCTL; depctl.b.epena = 1; depctl.b.cnak = 1; regs->DOEPCTL = depctl; } void { // Find the appropriate set of endpoint registers volatile USB_OTG_INEPREGS* regs = &data->core->INEP_REGS[ep.number]; // Calculate number of packets (if size == 0 an empty packet will be sent) int maxpacket = regs->DIEPCTL.b.mps; int packets = (size + maxpacket - 1) / maxpacket; if (!packets) packets = 1; // Set up data desination if (data->use_dma) regs->DIEPDMA = buf; else data->state->endpoints[ep.number].txaddr = (u32*)buf; USB_OTG_DEPXFRSIZ_TypeDef deptsiz = { .b = { .pktcnt = packets, .xfersize = size } }; regs->DIEPTSIZ = deptsiz; // Enable the endpoint USB_OTG_DEPCTL_TypeDef depctl = regs->DIEPCTL; depctl.b.epena = 1; depctl.b.cnak = 1; regs->DIEPCTL = depctl; // Start pushing data into the FIFO (must be done after enabling the endpoint) if (!data->use_dma) data->core->DREGS.DIEPEMPMSK.ep.in |= (1 << ep.number); } void synopsysotg_set_stall(const , union synopsysotg_endpoint_number ep, int stall) { if data->core->INEP_REGS[ep.number].DIEPCTL.b.stall = !!stall; else data->core->OUTEP_REGS[ep.number].DOEPCTL.b.stall = !!stall; } void { USB_OTG_DEPCTL_TypeDef depctl = { .b = { } }; if { if { // Urgh, someone was still babbling on our IN pipe, and now we have some // old crap in the FIFO. Disable the endpoint, to make sure nobody will // fetch any more old crap while we're trying to get rid of it. data->core->INEP_REGS[ep.number].DIEPCTL.b.epdis = 1; while (!(data->core->INEP_REGS[ep.number].DIEPINT.b.epdisabled)); // Wait for any DMA activity to stop, to make sure nobody will touch the FIFO. while (!data->core->GREGS.GRSTCTL.b.ahbidle); // Flush it all the way down! USB_OTG_GRSTCTL_TypeDef grstctl = { .b = { .txfnum = ep.number, .txfflsh = 1 } }; data->core->GREGS.GRSTCTL = grstctl; while (data->core->GREGS.GRSTCTL.b.txfflsh); } // Reset the transfer size register. Not strictly neccessary, but can't hurt. data->core->INEP_REGS[ep.number].DIEPTSIZ.d32 = 0; data->core->INEP_REGS[ep.number].DIEPCTL = depctl; // Mask interrupts for this endpoint data->core->DREGS.DAINTMSK.ep.in &= ~(1 << ep.number); } else { // We can't really do much about in-flight OUT requests except for ignoring them. data->core->OUTEP_REGS[ep.number].DOEPTSIZ.d32 = 0; data->core->OUTEP_REGS[ep.number].DOEPCTL = depctl; // Mask interrupts for this endpoint data->core->DREGS.DAINTMSK.ep.out &= ~(1 << ep.number); } } void synopsysotg_configure_ep(const , union synopsysotg_endpoint_number ep, enum synopsysotg_endpoint_type type, int maxpacket) { // Reset the endpoint, just in case someone left it in a dirty state. synopsysotg_unconfigure_ep(data, ep); // Write the new configuration and unmask interrupts for the endpoint USB_OTG_DEPCTL_TypeDef depctl = { .b = { .usbactep = 1, .eptype = type, .mps = maxpacket, .txfnum = ep.number } }; if { data->core->INEP_REGS[ep.number].DIEPCTL = depctl; data->core->DREGS.DAINTMSK.ep.in |= (1 << ep.number); } else { data->core->OUTEP_REGS[ep.number].DOEPCTL = depctl; data->core->DREGS.DAINTMSK.ep.out |= (1 << ep.number); } } void synopsysotg_ep0_start_rx(const , int non_setup) { // If we don't expect a non-SETUP packet, we can stall the OUT pipe, // SETUP packets will ignore that. if (!non_setup) data->core->OUTEP_REGS[0].DOEPCTL.b.stall = 1; // Set up data desination if (data->use_dma) data->core->OUTEP_REGS[0].DOEPDMA = data->buffer; else data->state->endpoints[0].rxaddr = (u32*)data->buffer; USB_OTG_DEP0XFRSIZ_TypeDef deptsiz = { .b = { .supcnt = 3, .pktcnt = !!non_setup, .xfersize = 64 } }; data->core->OUTEP_REGS[0].DOEPTSIZ.d32 = deptsiz.d32; // Enable the endpoint USB_OTG_DEPCTL_TypeDef depctl = data->core->OUTEP_REGS[0].DOEPCTL; depctl.b.epena = 1; depctl.b.cnak = 1; data->core->OUTEP_REGS[0].DOEPCTL = depctl; } void synopsysotg_ep0_send_response(const , const void* buf, int len) { // Expect zero-length ACK synopsysotg_ep0_start_rx(data, 1); // Set up data source if (data->use_dma) data->core->INEP_REGS[0].DIEPDMA = buf; else data->state->endpoints[0].txaddr = buf; USB_OTG_DEP0XFRSIZ_TypeDef deptsiz = { .b = { .pktcnt = (len + 63) >> 6, .xfersize = len } }; data->core->INEP_REGS[0].DIEPTSIZ.d32 = deptsiz.d32; // Enable the endpoint USB_OTG_DEPCTL_TypeDef depctl = data->core->INEP_REGS[0].DIEPCTL; depctl.b.epena = 1; depctl.b.cnak = 1; data->core->INEP_REGS[0].DIEPCTL = depctl; // Start pushing data into the FIFO (must be done after enabling the endpoint) if (!data->use_dma) data->core->DREGS.DIEPEMPMSK.ep.in |= 1; } void synopsysotg_ep0_send_ack(const ) { // No more data stages to follow, set up the OUT pipe for a SETUP packet. synopsysotg_ep0_start_rx(data, 0); // Set up the IN pipe for a zero-length packet USB_OTG_DEP0XFRSIZ_TypeDef deptsiz = { .b = { .pktcnt = 1 } }; data->core->INEP_REGS[0].DIEPTSIZ.d32 = deptsiz.d32; // Enable the endpoint USB_OTG_DEPCTL_TypeDef depctl = data->core->INEP_REGS[0].DIEPCTL; depctl.b.epena = 1; depctl.b.cnak = 1; data->core->INEP_REGS[0].DIEPCTL = depctl; } void synopsysotg_ep0_expect_setup(const ) { // The next packet needs to be a SETUP, so lock out everything on the IN pipe. data->core->INEP_REGS[0].DIEPCTL.b.stall = 1; // Set up the OUT pipe for the SETUP packet, STALLing everythin else. synopsysotg_ep0_start_rx(data, 0); } static void synopsysotg_ep0_init(const ) { // Make sure both EP0 pipes are active. // (The hardware should take care of that, but who knows...) USB_OTG_DEPCTL_TypeDef depctl = { .b = { .usbactep = 1 } }; data->core->OUTEP_REGS[0].DOEPCTL = depctl; data->core->INEP_REGS[0].DIEPCTL = depctl; // Prime EP0 for the first setup packet. synopsysotg_ep0_expect_setup(data); } static void synopsysotg_unconfigure(const ) { // Notify a configuration and its active interface altsettings that it was just kicked out. int configid = data->state->current_configuration; const = data->configurations[configid - 1]; int i; for { = configuration->interfaces[i]; const = interface->altsettings[interface->current_altsetting]; if altsetting->unset_altsetting(data, i, interface->current_altsetting); } if configuration->unset_configuration(data, configid); } static void { // size < -1: do nothing at all (dangerous, you need to take care of priming EP0 yourself!) // size == -1: send STALL // size == 0: send ACK // size > 0: send <size> bytes at <addr>, then expect ACK const void* addr = NULL; int size = -1; switch { case SYNOPSYSOTG_CTRLREQ_BMREQUESTTYPE_TYPE_STANDARD: switch { case SYNOPSYSOTG_CTRLREQ_BMREQUESTTYPE_RECIPIENT_DEVICE: switch { case SYNOPSYSOTG_CTRLREQ_BREQUEST_GET_STATUS: if (buffer->setup.wLength != 2 || buffer->setup.wIndex || !data->state->current_address || buffer->setup.wValue) break; data->buffer->raw[0] = 0; data->buffer->raw[1] = 1; addr = data->buffer; size = 2; break; case SYNOPSYSOTG_CTRLREQ_BREQUEST_SET_ADDRESS: if (buffer->setup.wLength || buffer->setup.wIndex || buffer->setup.wValue > 127) break; data->state->current_address = buffer->setup.wValue; // We can already set the address here, the OTG will send the ACK with the old address. data->core->DREGS.DCFG.b.devaddr = data->state->current_address; size = 0; break; case SYNOPSYSOTG_CTRLREQ_BREQUEST_GET_DESCRIPTOR: if (!buffer->setup.wLength) break; switch { case SYNOPSYSOTG_DESCRIPTOR_TYPE_DEVICE: if ((buffer->setup.wValue & 0xff) || buffer->setup.wIndex) break; addr = data->devicedescriptor; size = data->devicedescriptor->bLength; break; case SYNOPSYSOTG_DESCRIPTOR_TYPE_CONFIGURATION: if (buffer->setup.wIndex || (buffer->setup.wValue & 0xff) >= data->configuration_count) break; addr = data->configurations[buffer->setup.wValue & 0xff]->descriptor; size = data->configurations[buffer->setup.wValue & 0xff]->descriptor->wTotalLength; break; case SYNOPSYSOTG_DESCRIPTOR_TYPE_STRING: if ((buffer->setup.wValue & 0xff) > data->stringdescriptor_count) break; addr = data->stringdescriptors[buffer->setup.wValue & 0xff]; size = data->stringdescriptors[buffer->setup.wValue & 0xff]->bLength; break; } if (size > buffer->setup.wLength) size = buffer->setup.wLength; break; case SYNOPSYSOTG_CTRLREQ_BREQUEST_GET_CONFIGURATION: if (buffer->setup.wLength != 1 || buffer->setup.wIndex || !data->state->current_address || buffer->setup.wValue) break; data->buffer->raw[0] = data->state->current_configuration; addr = data->buffer; size = 1; break; case SYNOPSYSOTG_CTRLREQ_BREQUEST_SET_CONFIGURATION: if (buffer->setup.wLength || buffer->setup.wIndex || !data->state->current_address || buffer->setup.wValue > data->configuration_count) break; if (data->state->current_configuration) synopsysotg_unconfigure(data); data->state->current_configuration = buffer->setup.wValue; if { // Notify the configuration and its interface default altsettings that it should set up stuff int configid = data->state->current_configuration; const = data->configurations[configid - 1]; if configuration->set_configuration(data, configid); int i; for { = configuration->interfaces[i]; interface->current_altsetting = 0; const = interface->altsettings[0]; if (altsetting->set_altsetting) altsetting->set_altsetting(data, i, 0); } } size = 0; break; default: break; } break; case SYNOPSYSOTG_CTRLREQ_BMREQUESTTYPE_RECIPIENT_INTERFACE: { if (!data->state->current_configuration) break; int configid = data->state->current_configuration; const = data->configurations[configid - 1]; if (buffer->setup.wIndex >= configuration->interface_count) break; int intfid = buffer->setup.wIndex; = configuration->interfaces[intfid]; switch { case SYNOPSYSOTG_CTRLREQ_BREQUEST_GET_INTERFACE: if (buffer->setup.wLength != 1 || buffer->setup.wValue) break; data->buffer->raw[0] = interface->current_altsetting; addr = data->buffer; size = 1; break; case SYNOPSYSOTG_CTRLREQ_BREQUEST_SET_INTERFACE: { if (buffer->setup.wLength || buffer->setup.wValue > interface->altsetting_count) break; const = interface->altsettings[interface->current_altsetting]; if altsetting->unset_altsetting(data, intfid, interface->current_altsetting); interface->current_altsetting = buffer->setup.wValue; altsetting = interface->altsettings[interface->current_altsetting]; if altsetting->set_altsetting(data, intfid, interface->current_altsetting); break; } default: break; } break; default: break; } } break; default: break; } // See comment at the top of this function if (size == -1) synopsysotg_ep0_expect_setup(data); else if (size == 0) synopsysotg_ep0_send_ack(data); else if (size > 0) synopsysotg_ep0_send_response(data, addr, size); } static void synopsysotg_handle_ep0_data(const , union synopsysotg_buffer* buffer, int size) { // We don't accept any commands that have an OUT payload. Just STALL it, no matter what it was. synopsysotg_ep0_expect_setup(data); } static const (const , union synopsysotg_endpoint_number ep, int* ifidx, int* epidx) { // Figure out who's currently owning a (hardware) endpoint. // Returns a pointer to the synopsysotg_endpoint struct, and sets *epidx to its index within its altsetting. // *ifidx will be set to the interface number within the current configuration that the altsetting belongs to. // If nobody currently owns the specified endpoint, return NULL (*epidx and *ifidx will contain garbage). int configid = data->state->current_configuration; if (!configid) return NULL; const = data->configurations[configid - 1]; for++) { const = configuration->interfaces[*ifidx]; const = interface->altsettings[interface->current_altsetting]; for++) { const = altsetting->endpoints[*epidx]; if (endpoint->number.byte == ep.byte) return endpoint; } } return NULL; } static void synopsysotg_kill_endpoint(const , union synopsysotg_endpoint_number ep) { // Hm, apparently someone forgot to shut down an endpoint. // Let's try our best at cleaning up the mess... if { USB_OTG_DEPCTL_TypeDef depctl = data->core->INEP_REGS[ep.number].DIEPCTL; depctl.b.epdis = 1; depctl.b.usbactep = 0; data->core->INEP_REGS[ep.number].DIEPCTL = depctl; data->core->DREGS.DAINTMSK.ep.in &= ~(1 << ep.number); } else { USB_OTG_DEPCTL_TypeDef depctl = data->core->OUTEP_REGS[ep.number].DOEPCTL; depctl.b.epdis = 1; depctl.b.usbactep = 0; data->core->OUTEP_REGS[ep.number].DOEPCTL = depctl; data->core->DREGS.DAINTMSK.ep.out &= ~(1 << ep.number); } } static void synopsysotg_irq(const ) { USB_OTG_GINTSTS_TypeDef gintsts = data->core->GREGS.GINTSTS; if { data->core->DREGS.DCFG.b.devaddr = 0; synopsysotg_ep0_init(data); data->state->current_address = 0; if (data->state->current_configuration) synopsysotg_unconfigure(data); data->state->current_configuration = 0; if (data->bus_reset) data->bus_reset(data, data->core->DREGS.DSTS.b.enumspd == 0); } if { // Device to memory part of the "software DMA" implementation, used to receive data if use_dma == 0. // Handle one packet at a time, the IRQ will re-trigger if there's something left. USB_OTG_GRXFSTS_TypeDef rxsts = data->core->GREGS.GRXSTSP; int ep = rxsts.b.chnum; int words = (rxsts.b.bcnt + 3) >> 2; while (words--) *data->state->endpoints[ep].rxaddr++ = data->core->DFIFO[0][0]; } if { USB_OTG_DAINT_TypeDef daint = data->core->DREGS.DAINT; int ep; for if) { USB_OTG_DIEPINTn_TypeDef epints = data->core->INEP_REGS[ep].DIEPINT; const = NULL; union synopsysotg_endpoint_number epnum = { .direction = SYNOPSYSOTG_ENDPOINT_DIRECTION_IN, .number = ep }; int epidx; int ifidx; if (ep) endpoint = synopsysotg_find_endpoint(data, epnum, &epidx, &ifidx); if { // Memory to device part of the "software DMA" implementation, used to transmit data if use_dma == 0. USB_OTG_DEPXFRSIZ_TypeDef deptsiz = data->core->INEP_REGS[ep].DIEPTSIZ; if (!deptsiz.b.pktcnt) data->core->DREGS.DIEPEMPMSK.ep.in &= ~(1 << ep); else { // Push data into the TX FIFO until we don't have anything left or the FIFO would overflow. int left = (deptsiz.b.xfersize + 3) >> 2; while { int words = data->core->INEP_REGS[ep].DTXFSTS.b.txfspcavail; if (words > left) words = left; if (!words) break; left -= words; while (words--) data->core->DFIFO[ep][0] = *data->state->endpoints[ep].txaddr++; } } } int bytesleft = data->core->INEP_REGS[ep].DIEPTSIZ.b.xfersize; if { // Hm, the host didn't fetch our EP0 IN packet, so we feel a bit offended. // Refuse to accept any transfers, until we get a new SETUP token. if (!ep) synopsysotg_ep0_expect_setup(data); else if (!endpoint) synopsysotg_kill_endpoint(data, epnum); else if (endpoint->timeout) endpoint->timeout(data, ifidx, epidx, bytesleft); } if { // If this was EP0 IN, stall the pipe. There will only ever be one transfer for each // SETUP transaction, and the next SETUP packet will clear the stall. if (!ep) data->core->INEP_REGS[0].DIEPCTL.b.stall = 1; else if (!endpoint) synopsysotg_kill_endpoint(data, epnum); else if (endpoint->xfer_complete) endpoint->xfer_complete(data, ifidx, epidx, bytesleft); } data->core->INEP_REGS[ep].DIEPINT = epints; } } if { USB_OTG_DAINT_TypeDef daint = data->core->DREGS.DAINT; int ep; for if) { USB_OTG_DOEPINTn_TypeDef epints = data->core->OUTEP_REGS[ep].DOEPINT; const = NULL; union synopsysotg_endpoint_number epnum = { .direction = SYNOPSYSOTG_ENDPOINT_DIRECTION_OUT, .number = ep }; int epidx; int ifidx; if (ep) endpoint = synopsysotg_find_endpoint(data, epnum, &epidx, &ifidx); if { USB_OTG_DEP0XFRSIZ_TypeDef deptsiz = { .d32 = data->core->OUTEP_REGS[0].DOEPTSIZ.d32 }; int back2back = 3 - deptsiz.b.supcnt; if { // Urgh, someone was still babbling on our IN pipe, and now we have some // old crap in the FIFO. Disable the endpoint, to make sure nobody will // fetch any more old crap while we're trying to get rid of it. data->core->INEP_REGS[ep].DIEPCTL.b.epdis = 1; while (!(data->core->INEP_REGS[ep].DIEPINT.b.epdisabled)); // Wait for any DMA activity to stop, to make sure nobody will touch the FIFO. while (!data->core->GREGS.GRSTCTL.b.ahbidle); // Flush it all the way down! USB_OTG_GRSTCTL_TypeDef grstctl = { .b = { .txfnum = ep, .txfflsh = 1 } }; data->core->GREGS.GRSTCTL = grstctl; while (data->core->GREGS.GRSTCTL.b.txfflsh); // Reset the transfer size register. Not strictly necessary, but can't hurt. data->core->INEP_REGS[ep].DIEPTSIZ.d32 = 0; } if { // Figure out the location of the newest SETUP packet if there were // multiple back to back ones. If there were more than 3 SETUP packets // in a row, the OTG will take care of it, so we're on the safe side here. void* addr = &data->buffer->raw[8 * (back2back - 1)]; union synopsysotg_buffer* buffer = (union synopsysotg_buffer*)addr; if) synopsysotg_handle_ep0_setup(data, buffer); } else if (!endpoint) synopsysotg_kill_endpoint(data, epnum); else if (endpoint->setup_received) endpoint->setup_received(data, ifidx, epidx, back2back); } else if { int bytesleft = data->core->INEP_REGS[ep].DIEPTSIZ.b.xfersize; if { if) synopsysotg_handle_ep0_data(data, data->buffer, 64 - bytesleft); } else if (!endpoint) synopsysotg_kill_endpoint(data, epnum); else if (endpoint->xfer_complete) endpoint->xfer_complete(data, ifidx, epidx, bytesleft); } data->core->OUTEP_REGS[ep].DOEPINT = epints; } } data->core->GREGS.GINTSTS = gintsts; } void { int i; // Initialize data struct data->state->current_address = 0; data->state->current_configuration = 0; // Enable OTG clocks and configure GPIO pins int irq; if { synopsysotg_hsdata = data; irq = OTG_HS_IRQn; RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN; GPIOB->AFR[1] = (GPIOB->AFR[1] & ~0xff000000) | 0xcc000000; GPIOB->MODER = (GPIOB->MODER & ~0xf0000000) | 0xa0000000; } else if { synopsysotg_fsdata = data; irq = OTG_FS_IRQn; RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; GPIOA->AFR[1] = (GPIOA->AFR[1] & ~0x000ff000) | 0x000aa000; GPIOA->MODER = (GPIOA->MODER & ~0x03c00000) | 0x02800000; } else return; // Disable IRQ during setup NVIC_DisableIRQ(irq); // Enable PHY clocks USB_OTG_PCGCCTL_TypeDef pcgcctl = { .b = {} }; data->core->PCGCCTL = pcgcctl; // Configure PHY type (must be done before reset) USB_OTG_GCCFG_TypeDef gccfg = { .b = { .disablevbussensing = 1, .pwdn = 0 } }; data->core->GREGS.GCCFG = gccfg; USB_OTG_GUSBCFG_TypeDef gusbcfg = { .b = { .force_dev = 1, .usbtrdtim = SYNOPSYSOTG_TURNAROUND } }; if (data->use_ulpi) gusbcfg.b.ulpi_utmi_sel = 1; else gusbcfg.b.physel = 1; data->core->GREGS.GUSBCFG = gusbcfg; // Reset the whole USB core USB_OTG_GRSTCTL_TypeDef grstctl = { .b = { .csftrst = 1 } }; while (!data->core->GREGS.GRSTCTL.b.ahbidle); data->core->GREGS.GRSTCTL = grstctl; while (data->core->GREGS.GRSTCTL.b.csftrst); while (!data->core->GREGS.GRSTCTL.b.ahbidle); // Soft disconnect USB_OTG_DCTL_TypeDef dctl = { .b = { .sftdiscon = 1 } }; data->core->DREGS.DCTL = dctl; // Configure the core USB_OTG_GAHBCFG_TypeDef gahbcfg = { .b = { .dmaenable = data->use_dma, .hburstlen = SYNOPSYSOTG_AHB_BURST_LEN, .glblintrmsk = 1 } }; if { gahbcfg.b.nptxfemplvl_txfemplvl = 1; gahbcfg.b.ptxfemplvl = 1; } data->core->GREGS.GAHBCFG = gahbcfg; data->core->GREGS.GUSBCFG = gusbcfg; gccfg.b.pwdn = 1; data->core->GREGS.GCCFG = gccfg; USB_OTG_DCFG_TypeDef dcfg = { .b = { .nzstsouthshk = 1 } }; data->core->DREGS.DCFG = dcfg; // Configure the FIFOs if { USB_OTG_DTHRCTL_TypeDef dthrctl = { .b = { .arb_park_en = 1, .rx_thr_en = 1, .iso_thr_en = 0, .non_iso_thr_en = 0, .rx_thr_len = SYNOPSYSOTG_AHB_THRESHOLD } }; data->core->DREGS.DTHRCTL = dthrctl; } int addr = data->fifosize; for { int size = data->txfifosize[i]; addr -= size; if { USB_OTG_TXFSIZ_TypeDef fsiz = { .b = { .startaddr = addr, .depth = size } }; if (!i) data->core->GREGS.DIEPTXF0_HNPTXFSIZ = fsiz; else data->core->GREGS.DIEPTXF[i - 1] = fsiz; } } // Set up interrupts USB_OTG_DOEPMSK_TypeDef doepmsk = { .b = { .xfercompl = 1, .setup = 1 } }; data->core->DREGS.DOEPMSK = doepmsk; USB_OTG_DIEPMSK_TypeDef diepmsk = { .b = { .xfercompl = 1, .timeout = 1 } }; data->core->DREGS.DIEPMSK = diepmsk; data->core->DREGS.DIEPEMPMSK.d32 = 0; USB_OTG_DAINT_TypeDef daintmsk = { .ep = { .in = 0b0000000000000001, .out = 0b0000000000000001 } }; data->core->DREGS.DAINTMSK = daintmsk; USB_OTG_GINTMSK_TypeDef gintmsk = { .b = { .usbreset = 1, .outepintr = 1, .inepintr = 1 } }; if (!data->use_dma) gintmsk.b.rxstsqlvl = 1; data->core->GREGS.GINTMSK = gintmsk; synopsysotg_flush_ints(data); NVIC_ClearPendingIRQ(irq); NVIC_EnableIRQ(irq); // Soft reconnect dctl.b.sftdiscon = 0; data->core->DREGS.DCTL = dctl; } void otg_fs_irqhandler() { if (synopsysotg_fsdata) synopsysotg_irq(synopsysotg_fsdata); else NVIC_DisableIRQ(OTG_FS_IRQn); } void otg_hs_irqhandler() { if (synopsysotg_hsdata) synopsysotg_irq(synopsysotg_hsdata); else NVIC_DisableIRQ(OTG_HS_IRQn); } |