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#include "embiosapp.h"

#define debug_printf(msg, args...) cprintf(3, msg, ##args)
#define timeout_expired(start, timeout) TIMEOUT_EXPIRED(start, timeout)

#define SDCI_REG(x) (*((uint32_t volatile*)(0x38b00000 + (x))))

#define SDCI_CTRL SDCI_REG(0x00)
#define SDCI_DCTRL SDCI_REG(0x04)
#define SDCI_CMD SDCI_REG(0x08)
#define SDCI_ARGU SDCI_REG(0x0c)
#define SDCI_STATE SDCI_REG(0x10)
#define SDCI_STAC SDCI_REG(0x14)
#define SDCI_DSTA SDCI_REG(0x18)
#define SDCI_FSTA SDCI_REG(0x1c)
#define SDCI_RESP0 SDCI_REG(0x20)
#define SDCI_RESP1 SDCI_REG(0x24)
#define SDCI_RESP2 SDCI_REG(0x28)
#define SDCI_RESP3 SDCI_REG(0x2c)
#define SDCI_CDIV SDCI_REG(0x30)
#define SDCI_SDIO_CSR SDCI_REG(0x34)
#define SDCI_IRQ SDCI_REG(0x38)
#define SDCI_IRQ_MASK SDCI_REG(0x3c)
#define SDCI_DATA SDCI_REG(0x40)
#define SDCI_DMAADDR SDCI_REG(0x44)
#define SDCI_DMASIZE SDCI_REG(0x48)
#define SDCI_DMADIR SDCI_REG(0x48)
#define SDCI_REG6C SDCI_REG(0x6c)

#define SDCI_CTRL_SDCIEN BIT(0)
#define SDCI_CTRL_CARD_TYPE_MASK BIT(1)
#define SDCI_CTRL_CARD_TYPE_SD 0
#define SDCI_CTRL_CARD_TYPE_MMC BIT(1)
#define SDCI_CTRL_BUS_WIDTH_MASK BITRANGE(2, 3)
#define SDCI_CTRL_BUS_WIDTH_1BIT 0
#define SDCI_CTRL_BUS_WIDTH_4BIT BIT(2)
#define SDCI_CTRL_BUS_WIDTH_8BIT BIT(3)
#define SDCI_CTRL_DMA_EN BIT(4)
#define SDCI_CTRL_L_ENDIAN BIT(5)
#define SDCI_CTRL_DMA_REQ_CON_MASK BIT(6)
#define SDCI_CTRL_DMA_REQ_CON_NEMPTY 0
#define SDCI_CTRL_DMA_REQ_CON_FULL BIT(6)
#define SDCI_CTRL_CLK_SEL_MASK BIT(7)
#define SDCI_CTRL_CLK_SEL_PCLK 0
#define SDCI_CTRL_CLK_SEL_SDCLK BIT(7)
#define SDCI_CTRL_BIT_8 BIT(8)
#define SDCI_CTRL_BIT_14 BIT(14)

#define SDCI_DCTRL_TXFIFORST BIT(0)
#define SDCI_DCTRL_RXFIFORST BIT(1)
#define SDCI_DCTRL_TRCONT_MASK BITRANGE(4, 5)
#define SDCI_DCTRL_TRCONT_TX BIT(4)
#define SDCI_DCTRL_BUS_TEST_MASK BITRANGE(6, 7)
#define SDCI_DCTRL_BUS_TEST_TX BIT(6)
#define SDCI_DCTRL_BUS_TEST_RX BIT(7)

#define SDCI_CDIV_CLKDIV_MASK BITRANGE(0, 7)
#define SDCI_CDIV_CLKDIV_2 BIT(0)
#define SDCI_CDIV_CLKDIV_4 BIT(1)
#define SDCI_CDIV_CLKDIV_8 BIT(2)
#define SDCI_CDIV_CLKDIV_16 BIT(3)
#define SDCI_CDIV_CLKDIV_32 BIT(4)
#define SDCI_CDIV_CLKDIV_64 BIT(5)
#define SDCI_CDIV_CLKDIV_128 BIT(6)
#define SDCI_CDIV_CLKDIV_256 BIT(7)

#define SDCI_CMD_CMD_NUM_MASK BITRANGE(0, 5)
#define SDCI_CMD_CMD_NUM_SHIFT 0
#define SDCI_CMD_CMD_NUM(x) (x)
#define SDCI_CMD_CMD_TYPE_MASK BITRANGE(6, 7)
#define SDCI_CMD_CMD_TYPE_BC 0
#define SDCI_CMD_CMD_TYPE_BCR BIT(6)
#define SDCI_CMD_CMD_TYPE_AC BIT(7)
#define SDCI_CMD_CMD_TYPE_ADTC (BIT(6) | BIT(7))
#define SDCI_CMD_CMD_RD_WR BIT(8)
#define SDCI_CMD_RES_TYPE_MASK BITRANGE(16, 18)
#define SDCI_CMD_RES_TYPE_NONE 0
#define SDCI_CMD_RES_TYPE_R1 BIT(16)
#define SDCI_CMD_RES_TYPE_R2 BIT(17)
#define SDCI_CMD_RES_TYPE_R3 (BIT(16) | BIT(17))
#define SDCI_CMD_RES_TYPE_R4 BIT(18)
#define SDCI_CMD_RES_TYPE_R5 (BIT(16) | BIT(18))
#define SDCI_CMD_RES_TYPE_R6 (BIT(17) | BIT(18))
#define SDCI_CMD_RES_BUSY BIT(19)
#define SDCI_CMD_RES_SIZE_MASK BIT(20)
#define SDCI_CMD_RES_SIZE_48 0
#define SDCI_CMD_RES_SIZE_136 BIT(20)
#define SDCI_CMD_NCR_NID_MASK BIT(21)
#define SDCI_CMD_NCR_NID_NCR 0
#define SDCI_CMD_NCR_NID_NID BIT(21)
#define SDCI_CMDSTR BIT(31)

#define SDCI_STATE_DAT_STATE_MASK BITRANGE(0, 3)
#define SDCI_STATE_DAT_STATE_IDLE 0
#define SDCI_STATE_DAT_STATE_DAT_RCV BIT(0)
#define SDCI_STATE_DAT_STATE_CRC_RCV BIT(1)
#define SDCI_STATE_DAT_STATE_DAT_END (BIT(0) | BIT(1))
#define SDCI_STATE_DAT_STATE_DAT_SET BIT(2)
#define SDCI_STATE_DAT_STATE_DAT_OUT (BIT(0) | BIT(2))
#define SDCI_STATE_DAT_STATE_CRC_TIME (BIT(1) | BIT(2))
#define SDCI_STATE_DAT_STATE_CRC_OUT (BIT(0) | BIT(1) | BIT(2))
#define SDCI_STATE_DAT_STATE_ENDB_OUT BIT(3)
#define SDCI_STATE_DAT_STATE_ENDB_STOD (BIT(0) | BIT(3))
#define SDCI_STATE_DAT_STATE_DAT_CRCR (BIT(1) | BIT(3))
#define SDCI_STATE_DAT_STATE_CARD_PRG (BIT(0) | BIT(1) | BIT(3))
#define SDCI_STATE_DAT_STATE_DAT_BUSY (BIT(2) | BIT(3))
#define SDCI_STATE_CMD_STATE_MASK (BIT(4) | BIT(5) | BIT(6))
#define SDCI_STATE_CMD_STATE_CMD_IDLE 0
#define SDCI_STATE_CMD_STATE_CMD_CMDO BIT(0)
#define SDCI_STATE_CMD_STATE_CMD_CRCO BIT(1)
#define SDCI_STATE_CMD_STATE_CMD_TOUT (BIT(0) | BIT(1))
#define SDCI_STATE_CMD_STATE_CMD_RESR BIT(2)
#define SDCI_STATE_CMD_STATE_CMD_INTV (BIT(0) | BIT(2))

#define SDCI_STAC_CLR_CMDEND BIT(2)
#define SDCI_STAC_CLR_BIT_3 BIT(3)
#define SDCI_STAC_CLR_RESEND BIT(4)
#define SDCI_STAC_CLR_DATEND BIT(6)
#define SDCI_STAC_CLR_DAT_CRCEND BIT(7)
#define SDCI_STAC_CLR_CRC_STAEND BIT(8)
#define SDCI_STAC_CLR_RESTOUTE BIT(15)
#define SDCI_STAC_CLR_RESENDE BIT(16)
#define SDCI_STAC_CLR_RESINDE BIT(17)
#define SDCI_STAC_CLR_RESCRCE BIT(18)
#define SDCI_STAC_CLR_WR_DATCRCE BIT(22)
#define SDCI_STAC_CLR_RD_DATCRCE BIT(23)
#define SDCI_STAC_CLR_RD_DATENDE0 BIT(24)
#define SDCI_STAC_CLR_RD_DATENDE1 BIT(25)
#define SDCI_STAC_CLR_RD_DATENDE2 BIT(26)
#define SDCI_STAC_CLR_RD_DATENDE3 BIT(27)
#define SDCI_STAC_CLR_RD_DATENDE4 BIT(28)
#define SDCI_STAC_CLR_RD_DATENDE5 BIT(29)
#define SDCI_STAC_CLR_RD_DATENDE6 BIT(30)
#define SDCI_STAC_CLR_RD_DATENDE7 BIT(31)

#define SDCI_DSTA_CMDRDY BIT(0)
#define SDCI_DSTA_CMDPRO BIT(1)
#define SDCI_DSTA_CMDEND BIT(2)
#define SDCI_DSTA_RESPRO BIT(3)
#define SDCI_DSTA_RESEND BIT(4)
#define SDCI_DSTA_DATPRO BIT(5)
#define SDCI_DSTA_DATEND BIT(6)
#define SDCI_DSTA_DAT_CRCEND BIT(7)
#define SDCI_DSTA_CRC_STAEND BIT(8)
#define SDCI_DSTA_DAT_BUSY BIT(9)
#define SDCI_DSTA_SDCLK_HOLD BIT(12)
#define SDCI_DSTA_DAT0_STATUS BIT(13)
#define SDCI_DSTA_WP_DECT_INPUT BIT(14)
#define SDCI_DSTA_RESTOUTE BIT(15)
#define SDCI_DSTA_RESENDE BIT(16)
#define SDCI_DSTA_RESINDE BIT(17)
#define SDCI_DSTA_RESCRCE BIT(18)
#define SDCI_DSTA_WR_CRC_STATUS_MASK BITRANGE(19, 21)
#define SDCI_DSTA_WR_CRC_STATUS_OK BIT(20)
#define SDCI_DSTA_WR_CRC_STATUS_TXERR (BIT(19) | BIT(21))
#define SDCI_DSTA_WR_CRC_STATUS_CARDERR (BIT(19) | BIT(20) | BIT(21))
#define SDCI_DSTA_WR_DATCRCE BIT(22)
#define SDCI_DSTA_RD_DATCRCE BIT(23)
#define SDCI_DSTA_RD_DATENDE0 BIT(24)
#define SDCI_DSTA_RD_DATENDE1 BIT(25)
#define SDCI_DSTA_RD_DATENDE2 BIT(26)
#define SDCI_DSTA_RD_DATENDE3 BIT(27)
#define SDCI_DSTA_RD_DATENDE4 BIT(28)
#define SDCI_DSTA_RD_DATENDE5 BIT(29)
#define SDCI_DSTA_RD_DATENDE6 BIT(30)
#define SDCI_DSTA_RD_DATENDE7 BIT(31)

#define SDCI_FSTA_RX_FIFO_EMPTY BIT(0)
#define SDCI_FSTA_RX_FIFO_FULL BIT(1)
#define SDCI_FSTA_TX_FIFO_EMPTY BIT(2)
#define SDCI_FSTA_TX_FIFO_FULL BIT(3)

#define SDCI_SDIO_CSR_SDIO_RW_EN BIT(0)
#define SDCI_SDIO_CSR_SDIO_INT_EN BIT(1)
#define SDCI_SDIO_CSR_SDIO_RW_REQ BIT(2)
#define SDCI_SDIO_CSR_SDIO_RW_STOP BIT(3)
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MASK BIT(4)
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_MORE 0
#define SDCI_SDIO_CSR_SDIO_INT_PERIOD_XACT BIT(4)

#define SDCI_IRQ_DAT_DONE_INT BIT(0)
#define SDCI_IRQ_IOCARD_IRQ_INT BIT(1)
#define SDCI_IRQ_READ_WAIT_INT BIT(2)

#define SDCI_IRQ_MASK_MASK_DAT_DONE_INT BIT(0)
#define SDCI_IRQ_MASK_MASK_IOCARD_IRQ_INT BIT(1)
#define SDCI_IRQ_MASK_MASK_READ_WAIT_INT BIT(2)

#define SDCI_DMADIR_DIRECTION_MASK BIT(0)
#define SDCI_DMADIR_DIRECTION_WRITE 0
#define SDCI_DMADIR_DIRECTION_READ BIT(0)

#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SLEEP_AWAKE 5
#define MMC_CMD_SWITCH 6
#define MMC_CMD_SELECT_CARD 7
#define MMC_CMD_SEND_EXT_CSD 8
#define MMC_CMD_SEND_CSD 9
#define MMC_CMD_SEND_CID 10
#define MMC_CMD_READ_DAT_UNTIL_STOP 11
#define MMC_CMD_STOP_TRANSMISSION 12
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_BUSTEST_R 14
#define MMC_CMD_GO_INAVTIVE_STATE 15
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_BUSTEST_W 19
#define MMC_CMD_WRITE_DAT_UNTIL_STOP 20
#define MMC_CMD_SET_BLOCK_COUNT 23
#define MMC_CMD_WRITE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_PROGRAM_CID 26
#define MMC_CMD_PROGRAM_CSD 27
#define MMC_CMD_SET_WRITE_PROT 28
#define MMC_CMD_CLR_WRITE_PROT 29
#define MMC_CMD_SEND_WRITE_PROT 30
#define MMC_CMD_ERASE_GROUP_START 35
#define MMC_CMD_ERASE_GROUP_END 36
#define MMC_CMD_ERASE 38
#define MMC_CMD_FAST_IO 39
#define MMC_CMD_GO_IRQ_STATE 40
#define MMC_CMD_LOCK_UNLOCK 42
#define MMC_CMD_APP_CMD 55
#define MMC_CMD_GEN_CMD 56
#define MMC_CMD_CEATA_RW_MULTIPLE_REG 60
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK 61

#define MMC_CMD_SEND_OP_COND_OCR_MASK BITRANGE(0, 31)
#define MMC_CMD_SEND_OP_COND_OCR_SHIFT 0
#define MMC_CMD_SEND_OP_COND_OCR(x) (x)

#define MMC_CMD_SET_RELATIVE_ADDR_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SET_RELATIVE_ADDR_RCA_SHIFT 16
#define MMC_CMD_SET_RELATIVE_ADDR_RCA(x) ((x) << 16)

#define MMC_CMD_SET_DSR_DSR_MASK BITRANGE(16, 31)
#define MMC_CMD_SET_DSR_DSR_SHIFT 16
#define MMC_CMD_SET_DSR_DSR(x) ((x) << 16)

#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_MASK BIT(15)
#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_AWAKE 0
#define MMC_CMD_SLEEP_AWAKE_SLEEP_AWAKE_SLEEP BIT(15)
#define MMC_CMD_SLEEP_AWAKE_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SLEEP_AWAKE_RCA_SHIFT 16
#define MMC_CMD_SLEEP_AWAKE_RCA(x) ((x) << 16)

#define MMC_CMD_SWITCH_ACCESS_MASK BITRANGE(24, 25);
#define MMC_CMD_SWITCH_ACCESS_CMDSET 0
#define MMC_CMD_SWITCH_ACCESS_SET_BITS BIT(24)
#define MMC_CMD_SWITCH_ACCESS_CLEAR_BITS BIT(25)
#define MMC_CMD_SWITCH_ACCESS_WRITE_BYTE (BIT(24) | BIT(25))
#define MMC_CMD_SWTICH_INDEX_MASK BITRANGE(16, 23);
#define MMC_CMD_SWITCH_INDEX_SHIFT 16
#define MMC_CMD_SWITCH_INDEX(x) ((x) << 16)
#define MMC_CMD_SWTICH_VALUE_MASK BITRANGE(8, 15);
#define MMC_CMD_SWITCH_VALUE_SHIFT 8
#define MMC_CMD_SWITCH_VALUE(x) ((x) << 8)
#define MMC_CMD_SWTICH_CMDSET_MASK BITRANGE(0, 2);
#define MMC_CMD_SWITCH_CMDSET_STANDARD_MMC 0

#define MMC_CMD_SELECT_CARD_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SELECT_CARD_RCA_SHIFT 16
#define MMC_CMD_SELECT_CARD_RCA(x) ((x) << 16)

#define MMC_CMD_SEND_CSD_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SEND_CSD_RCA_SHIFT 16
#define MMC_CMD_SEND_CSD_RCA(x) ((x) << 16)

#define MMC_CMD_SEND_CID_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SEND_CID_RCA_SHIFT 16
#define MMC_CMD_SEND_CID_RCA(x) ((x) << 16)

#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS_SHIFT 0
#define MMC_CMD_READ_DAT_UNTIL_STOP_ADDRESS(x) (x)

#define MMC_CMD_SEND_STATUS_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_SEND_STATUS_RCA_SHIFT 16
#define MMC_CMD_SEND_STATUS_RCA(x) ((x) << 16)

#define MMC_CMD_GO_INACTIVE_STATE_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_GO_INACTIVE_STATE_RCA_SHIFT 16
#define MMC_CMD_GO_INACTIVE_STATE_RCA(x) ((x) << 16)

#define MMC_CMD_SET_BLOCKLEN_LENGTH_MASK BITRANGE(0, 31)
#define MMC_CMD_SET_BLOCKLEN_LENGTH_SHIFT 0
#define MMC_CMD_SET_BLOCKLEN_LENGTH(x) (x)

#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS_SHIFT 0
#define MMC_CMD_READ_SINGLE_BLOCK_ADDRESS(x) (x)

#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS_SHIFT 0
#define MMC_CMD_READ_MULTIPLE_BLOCK_ADDRESS(x) (x)

#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS_SHIFT 0
#define MMC_CMD_WRITE_DAT_UNTIL_STOP_ADDRESS(x) (x)

#define MMC_CMD_SET_BLOCK_COUNT_RELIABLE BIT(31)
#define MMC_CMD_SET_BLOCK_COUNT_COUNT_MASK BITRANGE(0, 15)
#define MMC_CMD_SET_BLOCK_COUNT_COUNT_SHIFT 0
#define MMC_CMD_SET_BLOCK_COUNT_COUNT(x) (x)

#define MMC_CMD_WRITE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_WRITE_BLOCK_ADDRESS_SHIFT 0
#define MMC_CMD_WRITE_BLOCK_ADDRESS(x) (x)

#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS_SHIFT 0
#define MMC_CMD_WRITE_MULTIPLE_BLOCK_ADDRESS(x) (x)

#define MMC_CMD_SET_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_SET_WRITE_PROT_ADDRESS_SHIFT 0
#define MMC_CMD_SET_WRITE_PROT_ADDRESS(x) (x)

#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_CLR_WRITE_PROT_ADDRESS_SHIFT 0
#define MMC_CMD_CLR_WRITE_PROT_ADDRESS(x) (x)

#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_SEND_WRITE_PROT_ADDRESS_SHIFT 0
#define MMC_CMD_SEND_WRITE_PROT_ADDRESS(x) (x)

#define MMC_CMD_ERASE_GROUP_START_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_ERASE_GROUP_START_ADDRESS_SHIFT 0
#define MMC_CMD_ERASE_GROUP_START_ADDRESS(x) (x)

#define MMC_CMD_ERASE_GROUP_END_ADDRESS_MASK BITRANGE(0, 31)
#define MMC_CMD_ERASE_GROUP_END_ADDRESS_SHIFT 0
#define MMC_CMD_ERASE_GROUP_END_ADDRESS(x) (x)

#define MMC_CMD_FAST_IO_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_FAST_IO_RCA_SHIFT 16
#define MMC_CMD_FAST_IO_RCA(x) ((x) << 16)
#define MMC_CMD_FAST_IO_DIRECTION_MASK BIT(15)
#define MMC_CMD_FAST_IO_DIRECTION_READ 0
#define MMC_CMD_FAST_IO_DIRECTION_WRITE BIT(15)
#define MMC_CMD_FAST_IO_ADDRESS_MASK BITRANGE(8, 14)
#define MMC_CMD_FAST_IO_ADDRESS_SHIFT 8
#define MMC_CMD_FAST_IO_ADDRESS(x) ((x) << 8)
#define MMC_CMD_FAST_IO_DATA_MASK BITRANGE(0, 7)
#define MMC_CMD_FAST_IO_DATA_SHIFT 0
#define MMC_CMD_FAST_IO_DATA(x) (x)

#define MMC_CMD_APP_CMD_RCA_MASK BITRANGE(16, 31)
#define MMC_CMD_APP_CMD_RCA_SHIFT 16
#define MMC_CMD_APP_CMD_RCA(x) ((x) << 16)

#define MMC_CMD_GEN_CMD_DIRECTION_MASK BIT(0)
#define MMC_CMD_GEN_CMD_DIRECTION_READ 0
#define MMC_CMD_GEN_CMD_DIRECTION_WRITE BIT(0)

#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_MASK BIT(31)
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ 0
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_WRITE BIT(31)
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_MASK BITRANGE(16, 23)
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS_SHIFT 16
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(x) ((x) << 16)
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_MASK BITRANGE(0, 7)
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT_SHIFT 0
#define MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(x) (x)

#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_MASK BIT(31)
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_READ 0
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_DIRECTION_WRITE BIT(31)
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_MASK BITRANGE(0, 15)
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT_SHIFT 0
#define MMC_CMD_CEATA_RW_MULTIPLE_BLOCK_COUNT(x) (x)

#define MMC_CMD_SWITCH_FIELD_ERASE_GROUP_DEF 175
#define MMC_CMD_SWITCH_FIELD_BOOT_BUS_WIDTH 177
#define MMC_CMD_SWITCH_FIELD_BOOT_CONFIG 179
#define MMC_CMD_SWITCH_FIELD_ERASED_MEM_CONT 181
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH 183
#define MMC_CMD_SWITCH_FIELD_HS_TIMING 185
#define MMC_CMD_SWITCH_FIELD_POWER_CLASS 187
#define MMC_CMD_SWITCH_FIELD_CMD_SET_REV 189
#define MMC_CMD_SWITCH_FIELD_CMD_SET 191
#define MMC_CMD_SWITCH_FIELD_EXT_CSD_REV 192
#define MMC_CMD_SWITCH_FIELD_CSD_STRUCTURE 194
#define MMC_CMD_SWITCH_FIELD_CARD_TYPE 196
#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_195 200
#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_195 201
#define MMC_CMD_SWITCH_FIELD_PWR_CL_52_360 202
#define MMC_CMD_SWITCH_FIELD_PWR_CL_26_360 203
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_4_26 205
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_4_26 206
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_26_4_52 207
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_26_4_52 208
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_R_8_52 209
#define MMC_CMD_SWITCH_FIELD_MIN_PERF_W_8_52 210
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_0 212
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_1 213
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_2 214
#define MMC_CMD_SWITCH_FIELD_SEC_COUNT_3 215
#define MMC_CMD_SWITCH_FIELD_S_A_TIMEOUT 217
#define MMC_CMD_SWITCH_FIELD_S_C_VCCQ 219
#define MMC_CMD_SWITCH_FIELD_S_C_VCC 220
#define MMC_CMD_SWITCH_FIELD_HC_WP_GRP_SIZE 221
#define MMC_CMD_SWITCH_FIELD_REL_WR_SEC_C 222
#define MMC_CMD_SWITCH_FIELD_ERASE_TIMEOUT_MULT 223
#define MMC_CMD_SWITCH_FIELD_HC_ERASE_GRP_SIZE 224
#define MMC_CMD_SWITCH_FIELD_ACC_SIZE 225
#define MMC_CMD_SWITCH_FIELD_BOOT_SIZE_MULTI 226
#define MMC_CMD_SWITCH_FIELD_S_CMD_SET 504

#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT 0
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT 1
#define MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT 2

#define MMC_CMD_SWITCH_FIELD_HS_TIMING_LOW_SPEED 0
#define MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED 1

#define MMC_STATUS_APP_CMD BIT(5)
#define MMC_STATUS_SWITCH_ERROR BIT(7)
#define MMC_STATUS_READY_FOR_DATA BIT(8)
#define MMC_STATUS_CURRENT_STATE_MASK BITRANGE(9, 12)
#define MMC_STATUS_CURRENT_STATE_IDLE 0
#define MMC_STATUS_CURRENT_STATE_READY BIT(9)
#define MMC_STATUS_CURRENT_STATE_IDENT BIT(10)
#define MMC_STATUS_CURRENT_STATE_STBY (BIT(9) | BIT(10))
#define MMC_STATUS_CURRENT_STATE_TRAN BIT(11)
#define MMC_STATUS_CURRENT_STATE_DATA (BIT(9) | BIT(11))
#define MMC_STATUS_CURRENT_STATE_RCV (BIT(10) | BIT(11))
#define MMC_STATUS_CURRENT_STATE_PRG (BIT(9) | BIT(10) | BIT(11))
#define MMC_STATUS_CURRENT_STATE_DIS BIT(12)
#define MMC_STATUS_CURRENT_STATE_BTST (BIT(9) | BIT(12))
#define MMC_STATUS_CURRENT_STATE_SLP (BIT(10) | BIT(12))
#define MMC_STATUS_ERASE_RESET BIT(13)
#define MMC_STATUS_WP_ERASE_SKIP BIT(15)
#define MMC_STATUS_CID_CSD_OVERWRITE BIT(16)
#define MMC_STATUS_OVERRUN BIT(17)
#define MMC_STATUS_UNDERRUN BIT(18)
#define MMC_STATUS_ERROR BIT(19)
#define MMC_STATUS_CC_ERROR BIT(20)
#define MMC_STATUS_CARD_ECC_FAILED BIT(21)
#define MMC_STATUS_ILLEGAL_COMMAND BIT(22)
#define MMC_STATUS_COM_CRC_ERROR BIT(23)
#define MMC_STATUS_LOCK_UNLOCK_FAILED BIT(24)
#define MMC_STATUS_CARD_IS_LOCKED BIT(25)
#define MMC_STATUS_WP_VIOLATION BIT(26)
#define MMC_STATUS_ERASE_PARAM BIT(27)
#define MMC_STATUS_ERASE_SEQ_ERROR BIT(28)
#define MMC_STATUS_BLOCK_LEN_ERROR BIT(29)
#define MMC_STATUS_ADDRESS_MISALIGN BIT(30)
#define MMC_STATUS_ADDRESS_OUT_OF_RANGE BIT(31)

#define MMC_OCR_170_195 BIT(7)
#define MMC_OCR_200_260 BITRANGE(8, 14)
#define MMC_OCR_270_360 BITRANGE(15, 23)
#define MMC_OCR_ACCESS_MODE_MASK BITRANGE(29, 30);
#define MMC_OCR_ACCESS_MODE_BYTE 0
#define MMC_OCR_ACCESS_MODE_SECTOR BIT(30)
#define MMC_OCR_POWER_UP_DONE BIT(31)

#define POWERUP_TIMEOUT 30000000
#define COMMAND_TIMEOUT 1000000
#define DAT_NONBUSY_TIMEOUT 5000000
#define CEATA_READ_BUF ((void*)0x08100000)
#define HDD_MMC_RCA 1

/*
uint32_t sub_800F69C()
{
    return SDCI_CTRL;
}

uint32_t sub_800FA14()
{
    return SDCI_STATE;
}

uint32_t sub_800FA00()
{
    return SDCI_RESP0;
}

uint32_t sub_800F3D8()
{
    return SDCI_IRQ;
}

uint32_t mmc_read_dsta()
{
    return SDCI_DSTA;
}

uint32_t sub_802A44C(uint32_t arg_1, uint32_t arg_2, uint32_t arg_3)
{
    if (arg_2 == 1)
    {
        if (arg_3 == 0) arg_2 = 0xe;
        else if (arg_3 == 1) arg_2 = 0xf;
    }
    arg_2 &= 0xff;
    *((uint32_t volatile*)0x3cf00200) = ((arg_1 >> 3) << 16) | ((arg_1 & 7) << 8) | arg_2;
    return 0;
}
*/

bool mmc_dsta_check_rx_success(bool check_crc)
{
    bool rc = true;
    uint32_t dsta = SDCI_DSTA;
    if (dsta & SDCI_DSTA_RESTOUTE)
    {
        debug_printf("mCS: response timeout error\n");
        rc = false;
    }
    if (dsta & SDCI_DSTA_RESENDE)
    {
        debug_printf("mCS: response end bit error\n");
        rc = false;
    }
    if (dsta & SDCI_DSTA_RESINDE)
    {
        debug_printf("mCS: response index error\n");
        rc = false;
    }
    if (check_crc)
    {
        if (dsta & SDCI_DSTA_RESCRCE)
        {
            debug_printf("mCS: response CRC error\n");
            rc = false;
        }
    }
    return rc;
}

bool mmc_send_command(uint32_t cmd, uint32_t arg, uint32_t* result, int timeout)
{
    debug_printf("%08X %08X\n", cmd, arg);
    long starttime = USEC_TIMER;
    while ((SDCI_STATE & SDCI_STATE_CMD_STATE_MASK) != SDCI_STATE_CMD_STATE_CMD_IDLE)
        if (timeout_expired(starttime, timeout))
        {
            debug_printf("mC: timed out waiting for controller to go idle");
            return false;
        }
    SDCI_STAC = SDCI_STAC_CLR_CMDEND | SDCI_STAC_CLR_BIT_3
              | SDCI_STAC_CLR_RESEND | SDCI_STAC_CLR_DATEND
              | SDCI_STAC_CLR_DAT_CRCEND | SDCI_STAC_CLR_CRC_STAEND
              | SDCI_STAC_CLR_RESTOUTE | SDCI_STAC_CLR_RESENDE
              | SDCI_STAC_CLR_RESINDE | SDCI_STAC_CLR_RESCRCE
              | SDCI_STAC_CLR_WR_DATCRCE | SDCI_STAC_CLR_RD_DATCRCE
              | SDCI_STAC_CLR_RD_DATENDE0 | SDCI_STAC_CLR_RD_DATENDE1
              | SDCI_STAC_CLR_RD_DATENDE2 | SDCI_STAC_CLR_RD_DATENDE3
              | SDCI_STAC_CLR_RD_DATENDE4 | SDCI_STAC_CLR_RD_DATENDE5
              | SDCI_STAC_CLR_RD_DATENDE6 | SDCI_STAC_CLR_RD_DATENDE7;
    SDCI_ARGU = arg;
    SDCI_CMD = cmd;
    if (!(SDCI_DSTA & SDCI_DSTA_CMDRDY))
    {
        debug_printf("mC: MMC_DSTA_CMDRDY not set after setting command/argument (DSTA = 0x%08x)\n", SDCI_DSTA);
        return false;
    }
    SDCI_CMD = cmd | SDCI_CMDSTR;
    udelay(1000);
    while (!(SDCI_DSTA & SDCI_DSTA_CMDEND))
        if (timeout_expired(starttime, timeout))
        {
            debug_printf("mC: timed out waiting for MMC_DSTA_CMDEND\n");
            return false;
        }
    if ((cmd & SDCI_CMD_RES_TYPE_MASK) != SDCI_CMD_RES_TYPE_NONE)
    {
        while (!(SDCI_DSTA & SDCI_DSTA_RESEND))
            if (timeout_expired(starttime, timeout))
            {
                debug_printf("mC: timed out waiting for MMC_DSTA_RESEND\n");
                return false;
            }
        if (cmd & SDCI_CMD_RES_BUSY)
        {
            while (SDCI_DSTA & SDCI_DSTA_DAT_BUSY)
                if (timeout_expired(starttime, DAT_NONBUSY_TIMEOUT))
                {
                    debug_printf("mC: timed out waiting for !MMC_DSTA_DAT_BUSY\n");
                    return false;
                }
        }
    }
    if (!mmc_dsta_check_rx_success((cmd & SDCI_CMD_RES_SIZE_MASK) == SDCI_CMD_RES_SIZE_136))
    {
        debug_printf("mC: command failed\n");
        return false;
    }
    if (result) *result = SDCI_RESP0;
    return true;
}

bool mmc_get_card_status(uint32_t* result)
{
    if (mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_STATUS)
                       | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
                       | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                         MMC_CMD_SEND_STATUS_RCA(HDD_MMC_RCA), result, COMMAND_TIMEOUT))
        return true;
    debug_printf("mGCS: SEND_STATUS failed\n");
    return false;
}

bool mmc_init()
{
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_GO_IDLE_STATE)
                        | SDCI_CMD_CMD_TYPE_BC | SDCI_CMD_RES_TYPE_NONE
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
                          0, NULL, COMMAND_TIMEOUT))
    {
        debug_printf("mI: GO IDLE failed\n");
        return false;
    }
    long startusec = USEC_TIMER;
    uint32_t result;
    do
    {
        if (timeout_expired(startusec, POWERUP_TIMEOUT))
        {
            debug_printf("mI: timed out waiting for drive to power up\n");
            return false;
        }
        sleep(1000);
        if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SEND_OP_COND)
                            | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R3
                            | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NID,
                              MMC_CMD_SEND_OP_COND_OCR(MMC_OCR_270_360), NULL, COMMAND_TIMEOUT))
        {
            debug_printf("mI: SEND OP COND failed\n");
            return false;
        }
        result = SDCI_RESP0;
    }
    while (!(result & MMC_OCR_POWER_UP_DONE));
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_ALL_SEND_CID)
                        | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R2
                        | SDCI_CMD_RES_SIZE_136 | SDCI_CMD_NCR_NID_NID,
                          0, NULL, COMMAND_TIMEOUT))
    {
        debug_printf("mI: ALL SEND CID failed\n");
        return false;
    }
    sleep(50000);
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SET_RELATIVE_ADDR)
                        | SDCI_CMD_CMD_TYPE_BCR | SDCI_CMD_RES_TYPE_R1
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_SET_RELATIVE_ADDR_RCA(HDD_MMC_RCA), NULL, COMMAND_TIMEOUT))
    {
        debug_printf("mI: SET_RELATIVE_ADDRESS failed\n");
        return false;
    }
    sleep(50000);
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SELECT_CARD)
                        | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_SELECT_CARD_RCA(HDD_MMC_RCA), NULL, COMMAND_TIMEOUT))
    {
        debug_printf("mI: SELECT CARD failed\n");
        return false;
    }
    sleep(50000);
    if (mmc_get_card_status(&result)
     && (result & MMC_STATUS_CURRENT_STATE_MASK) == MMC_STATUS_CURRENT_STATE_TRAN)
        return true;
    debug_printf("mI: card not in MMC TRAN state as expected\n");
    return false;
}

bool mmc_fastio_write(uint32_t addr, uint32_t data)
{
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
                        | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_FAST_IO_RCA(HDD_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_WRITE
                        | MMC_CMD_FAST_IO_ADDRESS(addr) | MMC_CMD_FAST_IO_DATA(data),
                          NULL, COMMAND_TIMEOUT))
    {
        debug_printf("cSTFR: FAST_IO Write failed\n");
        return false;
    }
}

bool mmc_fastio_read(uint32_t addr, uint32_t* data)
{
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_FAST_IO)
                        | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R4
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_FAST_IO_RCA(HDD_MMC_RCA) | MMC_CMD_FAST_IO_DIRECTION_READ
                        | MMC_CMD_FAST_IO_ADDRESS(addr), data, COMMAND_TIMEOUT))
    {
        debug_printf("cSTFR: FAST_IO Read failed\n");
        return false;
    }
}

uint32_t ceata_soft_reset()
{
    if (!mmc_fastio_write(6, 4))
    {
        debug_printf("ISR: Can't soft-reset device\n");
        return 0x5a;
    }
    udelay(1000);
    if (!mmc_fastio_write(6, 0))
    {
        debug_printf("ISR: Can't clear soft reset\n");
        return 0x5a;
    }
    sleep(100000);
    long startusec = USEC_TIMER;
    uint32_t thing;
    do
    {
        if (!mmc_fastio_read(0xf, &thing)) return 0x59;
        if (timeout_expired(startusec, POWERUP_TIMEOUT))
        {
            debug_printf("cSRst: Soft Reset timed out waiting for !MMC_DSTA_DAT_BUSY\n");
            return 0x5a;
        }
        sleep(50000);
    }
    while (thing & 0x80);
    return 0;
}

bool sub_800A224()
{
    uint32_t dsta = SDCI_DSTA;
    bool rc = true;
    if (dsta & (SDCI_DSTA_WR_DATCRCE | SDCI_DSTA_RD_DATCRCE))
    {
        if (dsta & SDCI_DSTA_WR_DATCRCE)
        {
            debug_printf("mDS: write data CRC response error\n");
            rc = false;
        }
        if (dsta & SDCI_DSTA_RD_DATCRCE)
        {
            debug_printf("mDS: read data CRC error\n");
            rc = false;
        }
        if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_TXERR)
        {
            debug_printf("mDS: write data CRC error\n");
            rc = false;
        }
        else if ((dsta & SDCI_DSTA_WR_CRC_STATUS_MASK) == SDCI_DSTA_WR_CRC_STATUS_CARDERR)
        {
            debug_printf("mDS: write data card CRC error\n");
            rc = false;
        }
    }
    if (dsta & (SDCI_DSTA_RD_DATENDE0 | SDCI_DSTA_RD_DATENDE1 | SDCI_DSTA_RD_DATENDE2
              | SDCI_DSTA_RD_DATENDE3 | SDCI_DSTA_RD_DATENDE4 | SDCI_DSTA_RD_DATENDE5
              | SDCI_DSTA_RD_DATENDE6 | SDCI_DSTA_RD_DATENDE7))
    {
        debug_printf("mDS: read data end bit error(s)\n");
        rc = false;
    }
    return rc;
}

bool mmc_read_multiple(uint32_t addr, uint8_t* dest, uint32_t size)
{
    if (size > 0x10)
    {
        debug_printf("mRM: read size exceeds FIFO depth\n");
        return false;
    }
    SDCI_DMASIZE = size;
    SDCI_DMADIR = SDCI_DMADIR_DIRECTION_READ;
    SDCI_DMAADDR = (uint32_t)CEATA_READ_BUF;
    SDCI_DCTRL = SDCI_DCTRL_TXFIFORST | SDCI_DCTRL_RXFIFORST;
    invalidate_dcache();
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_CEATA_RW_MULTIPLE_REG)
                        | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_CEATA_RW_MULTIPLE_REG_DIRECTION_READ
                        | MMC_CMD_CEATA_RW_MULTIPLE_REG_ADDRESS(addr & 0xfc)
                        | MMC_CMD_CEATA_RW_MULTIPLE_REG_COUNT(size & 0xfc), NULL, COMMAND_TIMEOUT))
    {
        debug_printf("mRM: READ MULTIPLE REGISTER(0x%x, 0x%x) failed\n", addr, size);
        return false;
    }
    long startusec = USEC_TIMER;
    while (!(SDCI_IRQ & SDCI_IRQ_DAT_DONE_INT))
        if (timeout_expired(startusec, COMMAND_TIMEOUT))
        {
            debug_printf("mRM: timed out waiting for transfer to complete\n");
            return false;
        }
    SDCI_IRQ = SDCI_IRQ_DAT_DONE_INT;
    if (!sub_800A224())
    {
        debug_printf("mRM: data transfer error(s)\n");
        return false;
    }
    memcpy(dest, CEATA_READ_BUF, size);
    return true;
}

bool ceata_init(int buswidth)
{
    uint32_t result;
    if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
                        | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1 
                        | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                          MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
                        | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_HS_TIMING)
                        | MMC_CMD_SWITCH_VALUE(MMC_CMD_SWITCH_FIELD_HS_TIMING_HIGH_SPEED),
                          &result, COMMAND_TIMEOUT))
    {
        debug_printf("cI: Set drive to MMC high speed failed\n");
        return false;
    }
    if (result & MMC_STATUS_SWITCH_ERROR)
    {
        debug_printf("cI: card failed HS_TIMING SWITCH\n");
        return false;
    }
    if (buswidth > 1)
    {
        int setting;
        if (buswidth == 4) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_4BIT;
        else if (buswidth == 8) setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_8BIT;
        else setting = MMC_CMD_SWITCH_FIELD_BUS_WIDTH_1BIT;
        if (!mmc_send_command(SDCI_CMD_CMD_NUM(MMC_CMD_SWITCH) | SDCI_CMD_RES_BUSY
                            | SDCI_CMD_CMD_TYPE_AC | SDCI_CMD_RES_TYPE_R1
                            | SDCI_CMD_RES_SIZE_48 | SDCI_CMD_NCR_NID_NCR,
                              MMC_CMD_SWITCH_ACCESS_WRITE_BYTE
                            | MMC_CMD_SWITCH_INDEX(MMC_CMD_SWITCH_FIELD_BUS_WIDTH)
                            | MMC_CMD_SWITCH_VALUE(setting), &result, COMMAND_TIMEOUT))
        {
            debug_printf("cI: SWITCH to %d-bit bus width failed\n", buswidth);
            return false;
        }
        if (result & MMC_STATUS_SWITCH_ERROR)
        {
            debug_printf("cI: card failed bus size SWITCH\n");
            return false;
        }
        if (buswidth == 4)
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_4BIT;
        else if (buswidth == 8)
            SDCI_CTRL = (SDCI_CTRL & ~SDCI_CTRL_BUS_WIDTH_MASK) | SDCI_CTRL_BUS_WIDTH_8BIT;
    }
    if (ceata_soft_reset())
    {
        debug_printf("cI: Soft Reset sequence error\n");
        return false;
    }
    uint8_t buffer[0x10];
    if (!mmc_read_multiple(0, buffer, 0x10))
    {
        debug_printf("cI: could not read CE-ATA task file\n");
        return false;
    }
    if (buffer[0xc] != 0xce || buffer[0xd] != 0xaa)
    {
        debug_printf("cI: CE-ATA signature missing (%x,%x)\n", buffer[0xc], buffer[0xd]);
        return false;
    }
    if (!mmc_fastio_write(6, 0))
    {
        debug_printf("ISR: CE-ATA interrupt enable failed\n");
        return false;
    }
    return true;
}

uint32_t hdd_init()
{
    clockgate_enable(9, true);
    *((uint32_t volatile*)0x38a00000) = 0;
    *((uint32_t volatile*)0x38700000) = 0;
    SDCI_REG6C = 0xa5;
    sleep(100000);
    if (SDCI_CTRL) return 0;
    *((uint32_t volatile*)0x3cf00380) = 0;
    *((uint32_t volatile*)0x3cf0010c) = 0xff;
    SDCI_CTRL = SDCI_CTRL_SDCIEN | SDCI_CTRL_CLK_SEL_SDCLK | SDCI_CTRL_BIT_8 | SDCI_CTRL_BIT_14;
    SDCI_CDIV = SDCI_CDIV_CLKDIV_256;
    *((uint32_t volatile*)0x3cf00200) = 0xb000f;
    SDCI_IRQ_MASK = 0;
    if (!mmc_init())
    {
        debug_printf("MMC init failed\n");
        return 0x5b;
    }
    SDCI_CDIV = SDCI_CDIV_CLKDIV_4;
    sleep(100000);
    if (!ceata_init(8))
    {
        debug_printf("CE-ATA init failed\n");
        return 0x5b;
    }
    return 0;
}