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Index: firmware/drivers/ata.c
===================================================================
--- firmware/drivers/ata.c	(revision 28885)
+++ firmware/drivers/ata.c	(working copy)
@@ -36,6 +36,71 @@
 
 #define SECTOR_SIZE     (512)
 
+#ifndef ATA_READ_REG
+#define ATA_READ_REG(reg) (reg)
+#endif
+#ifndef ATA_WRITE_REG
+#define ATA_WRITE_REG(reg, value) (reg) = (value)
+#endif
+
+#ifndef STATUS_BSY
+#define STATUS_BSY (0x80)
+#endif
+#ifndef STATUS_RDY
+#define STATUS_RDY (0x40)
+#endif
+#ifndef STATUS_DRQ
+#define STATUS_DRQ (0x08)
+#endif
+#ifndef STATUS_ERR
+#define STATUS_ERR (0x01)
+#endif
+#ifndef STATUS_DF
+#define STATUS_DF (0x20)
+#endif
+#ifndef ERROR_IDNF
+#define ERROR_IDNF (0x10)
+#endif
+#ifndef ERROR_ABRT
+#define ERROR_ABRT (0x04)
+#endif
+#ifndef WRITE_PATTERN1
+#define WRITE_PATTERN1 (0xa5)
+#endif
+#ifndef WRITE_PATTERN2
+#define WRITE_PATTERN2 (0x5a)
+#endif
+#ifndef WRITE_PATTERN3
+#define WRITE_PATTERN3 (0xaa)
+#endif
+#ifndef WRITE_PATTERN4
+#define WRITE_PATTERN4 (0x55)
+#endif
+#ifndef READ_PATTERN1
+#define READ_PATTERN1 (0xa5)
+#endif
+#ifndef READ_PATTERN2
+#define READ_PATTERN2 (0x5a)
+#endif
+#ifndef READ_PATTERN3
+#define READ_PATTERN3 (0xaa)
+#endif
+#ifndef READ_PATTERN4
+#define READ_PATTERN4 (0x55)
+#endif
+#ifndef READ_PATTERN1_MASK
+#define READ_PATTERN1_MASK (0xff)
+#endif
+#ifndef READ_PATTERN2_MASK
+#define READ_PATTERN2_MASK (0xff)
+#endif
+#ifndef READ_PATTERN3_MASK
+#define READ_PATTERN3_MASK (0xff)
+#endif
+#ifndef READ_PATTERN4_MASK
+#define READ_PATTERN4_MASK (0xff)
+#endif
+
 #define ATA_FEATURE     ATA_ERROR
 
 #define ATA_STATUS      ATA_COMMAND
Index: firmware/export/config/ipod6g.h
===================================================================
--- firmware/export/config/ipod6g.h	(revision 0)
+++ firmware/export/config/ipod6g.h	(revision 0)
@@ -0,0 +1,242 @@
+/*
+ * This config file is for iPod 6G / Classic
+ */
+#define TARGET_TREE /* this target is using the target tree system */
+
+#define IPOD_ARCH 1
+
+/* For Rolo and boot loader */
+#define MODEL_NUMBER 71
+
+#define MODEL_NAME   "Apple iPod Classic/6G"
+
+/* define this if you use an ATA controller */
+#define CONFIG_STORAGE STORAGE_ATA
+
+/* define this if the ATA controller and method of USB access support LBA48 */
+#define HAVE_LBA48
+
+/* define this if you have recording possibility */
+//#define HAVE_RECORDING
+
+/* Define bitmask of input sources - recordable bitmask can be defined
+   explicitly if different */
+#define INPUT_SRC_CAPS (SRC_CAP_LINEIN)
+
+/* define the bitmask of hardware sample rates */
+#define HW_SAMPR_CAPS   (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
+                       | SAMPR_CAP_96 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
+                       | SAMPR_CAP_64 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
+
+/* define the bitmask of recording sample rates */
+#define REC_SAMPR_CAPS  (SAMPR_CAP_88 | SAMPR_CAP_44 | SAMPR_CAP_22 | SAMPR_CAP_11 \
+                       | SAMPR_CAP_96 | SAMPR_CAP_48 | SAMPR_CAP_24 | SAMPR_CAP_12 \
+                       | SAMPR_CAP_64 | SAMPR_CAP_32 | SAMPR_CAP_16 | SAMPR_CAP_8)
+
+/* define this if you have a bitmap LCD display */
+#define HAVE_LCD_BITMAP
+
+/* define this if you can flip your LCD */
+//#define HAVE_LCD_FLIP
+
+/* define this if you have a colour LCD */
+#define HAVE_LCD_COLOR
+
+/* define this if you want album art for this target */
+#define HAVE_ALBUMART
+
+/* define this to enable bitmap scaling */
+#define HAVE_BMP_SCALING
+
+/* define this to enable JPEG decoding */
+#define HAVE_JPEG
+
+/* define this if you can invert the colours on your LCD */
+//#define HAVE_LCD_INVERT
+
+/* LCD stays visible without backlight - simulator hint */
+#define HAVE_TRANSFLECTIVE_LCD
+
+/* define this if you have access to the quickscreen */
+#define HAVE_QUICKSCREEN
+
+/* define this if you have access to the pitchscreen */
+#define HAVE_PITCHSCREEN
+
+/* define this if you would like tagcache to build on this target */
+#define HAVE_TAGCACHE
+
+/* define this if the unit uses a scrollwheel for navigation */
+#define HAVE_SCROLLWHEEL
+#define HAVE_WHEEL_ACCELERATION
+#define WHEEL_ACCEL_START 270
+#define WHEEL_ACCELERATION 3
+
+/* Define this if you can detect headphones */
+#define HAVE_HEADPHONE_DETECTION
+
+/* LCD dimensions */
+#define LCD_WIDTH  320
+#define LCD_HEIGHT 240
+#define LCD_DEPTH  16   /* pseudo 262.144 colors */
+#define LCD_PIXELFORMAT RGB565 /* rgb565 */
+
+/* Define this if the LCD can shut down */
+#define HAVE_LCD_SHUTDOWN
+
+/* Define this if your LCD can be enabled/disabled */
+#define HAVE_LCD_ENABLE
+
+/* Define this if your LCD can be put to sleep. HAVE_LCD_ENABLE
+   should be defined as well. */
+#ifndef BOOTLOADER
+//TODO: #define HAVE_LCD_SLEEP
+//TODO: #define HAVE_LCD_SLEEP_SETTING
+#endif
+
+#define CONFIG_KEYPAD IPOD_4G_PAD
+
+//#define AB_REPEAT_ENABLE
+//#define ACTION_WPSAB_SINGLE ACTION_WPS_BROWSE
+
+/* Define this to enable morse code input */
+#define HAVE_MORSE_INPUT
+
+/* Define this if you do software codec */
+#define CONFIG_CODEC SWCODEC
+
+/* define this if you have a real-time clock */
+#define CONFIG_RTC RTC_NANO2G
+
+/* Define if the device can wake from an RTC alarm */
+//#define HAVE_RTC_ALARM
+
+#define CONFIG_LCD LCD_IPOD6G
+
+/* Define the type of audio codec */
+//TODO: #define HAVE_WM8975
+
+#define HAVE_PCM_DMA_ADDRESS
+
+/* Define this for LCD backlight available */
+#define HAVE_BACKLIGHT
+#define HAVE_BACKLIGHT_BRIGHTNESS
+
+/* Define this if you have a software controlled poweroff */
+#define HAVE_SW_POWEROFF
+
+/* The number of bytes reserved for loadable codecs */
+#define CODEC_SIZE 0x100000
+
+/* The number of bytes reserved for loadable plugins */
+#define PLUGIN_BUFFER_SIZE 0x80000
+
+// TODO: Figure out real values
+#define BATTERY_CAPACITY_DEFAULT 400 /* default battery capacity */
+#define BATTERY_CAPACITY_MIN     300 /* min. capacity selectable */
+#define BATTERY_CAPACITY_MAX     500 /* max. capacity selectable */
+#define BATTERY_CAPACITY_INC      10 /* capacity increment */
+#define BATTERY_TYPES_COUNT        1 /* only one type */
+
+/* Hardware controlled charging with monitoring */
+#define CONFIG_CHARGING CHARGING_MONITOR
+
+/* define current usage levels */
+//TODO: #define CURRENT_NORMAL     21  /* playback @48MHz clock, backlight off */
+//TODO: #define CURRENT_BACKLIGHT  23  /* maximum brightness */
+
+/* define this if the unit can be powered or charged via USB */
+#define HAVE_USB_POWER
+
+/* Define this if your LCD can set contrast */
+//#define HAVE_LCD_CONTRAST
+
+/* Define Apple remote tuner */
+//#define CONFIG_TUNER IPOD_REMOTE_TUNER
+//#define HAVE_RDS_CAP
+
+/* The exact type of CPU */
+#define CONFIG_CPU S5L8702
+
+/* I2C interface */
+#define CONFIG_I2C I2C_S5L8702
+
+#define HAVE_USB_CHARGING_ENABLE
+
+/* The size of the flash ROM */
+#define FLASH_SIZE 0x400000
+
+/* Define this to the CPU frequency */
+//TODO: Figure out exact value
+#define CPU_FREQ        216000000
+
+/* define this if the hardware can be powered off while charging */
+#define HAVE_POWEROFF_WHILE_CHARGING
+
+/* Offset ( in the firmware file's header ) to the file CRC */
+#define FIRMWARE_OFFSET_FILE_CRC 0
+
+/* Offset ( in the firmware file's header ) to the real data */
+#define FIRMWARE_OFFSET_FILE_DATA 8
+
+/* Define this if you can read an absolute wheel position */
+#define HAVE_WHEEL_POSITION
+
+/* define this if the device has larger sectors when accessed via USB */
+/* (only relevant in disk.c, fat.c now always supports large virtual sectors) */
+#define MAX_LOG_SECTOR_SIZE 4096
+
+/* define this if the hard drive uses large physical sectors (ATA-7 feature) */
+/* and doesn't handle them in the drive firmware */
+#define MAX_PHYS_SECTOR_SIZE 4096
+
+/* Define this if you have adjustable CPU frequency */
+//TODO: #define HAVE_ADJUSTABLE_CPU_FREQ
+
+#define BOOTFILE_EXT "ipod"
+#define BOOTFILE "rockbox." BOOTFILE_EXT
+#define BOOTDIR "/.rockbox"
+
+/* Alternative bootfile extension - this is for encrypted images */
+#define BOOTFILE_EXT2 "ipodx"
+
+/* Define this for FM radio input available */
+#define HAVE_FMRADIO_IN
+
+/** Port-specific settings **/
+
+#if 0
+/* Main LCD contrast range and defaults */
+#define MIN_CONTRAST_SETTING        1
+#define MAX_CONTRAST_SETTING        30
+#define DEFAULT_CONTRAST_SETTING    19 /* Match boot contrast */
+#endif
+
+/* Main LCD backlight brightness range and defaults */
+#define MIN_BRIGHTNESS_SETTING      1
+#define MAX_BRIGHTNESS_SETTING      0x3f
+#define DEFAULT_BRIGHTNESS_SETTING  0x20
+
+/* USB defines */
+#define HAVE_USBSTACK
+//#define HAVE_USB_HID_MOUSE - broken?
+#define CONFIG_USBOTG USBOTG_S3C6400X
+#define USB_VENDOR_ID 0x05AC
+//TODO: This is still the Nano2G product ID. Figure out the real one.
+#define USB_PRODUCT_ID 0x1260
+#define USB_NUM_ENDPOINTS 5
+#define USE_ROCKBOX_USB
+#define USB_DEVBSS_ATTR __attribute__((aligned(16)))
+
+/* Define this if you can switch on/off the accessory power supply */
+#define HAVE_ACCESSORY_SUPPLY
+//#define IPOD_ACCESSORY_PROTOCOL
+//#define HAVE_SERIAL
+
+/* Define this, if you can switch on/off the lineout */
+#define HAVE_LINEOUT_POWEROFF
+
+#define USB_WRITE_BUFFER_SIZE (1024*64)
+
+/* Define this if a programmable hotkey is mapped */
+#define HAVE_HOTKEY
Index: firmware/export/cpu.h
===================================================================
--- firmware/export/cpu.h	(revision 28885)
+++ firmware/export/cpu.h	(working copy)
@@ -59,9 +59,12 @@
 #ifdef CPU_TCC780X
 #include "tcc780x.h"
 #endif
-#ifdef CPU_S5L870X
+#if CONFIG_CPU == S5L8700 || CONFIG_CPU == S5L8701
 #include "s5l8700.h"
 #endif
+#if CONFIG_CPU == S5L8702
+#include "s5l8702.h"
+#endif
 #if CONFIG_CPU == JZ4732
 #include "jz4740.h"
 #endif
Index: firmware/export/i2c-s5l8702.h
===================================================================
--- firmware/export/i2c-s5l8702.h	(revision 0)
+++ firmware/export/i2c-s5l8702.h	(revision 0)
@@ -0,0 +1,32 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: i2c-s5l8700.h 21533 2009-06-27 20:11:11Z bertrik $
+ *
+ * Copyright (C) 2009 by Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef _I2C_S5l8702_H
+#define _I2C_S5l8702_H
+
+#include "config.h"
+
+void i2c_init(void);
+int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data);
+int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data);
+
+#endif /* _I2C_S5l8702_H */
+
Index: firmware/export/s5l8702.h
===================================================================
--- firmware/export/s5l8702.h	(revision 0)
+++ firmware/export/s5l8702.h	(revision 0)
@@ -0,0 +1,608 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: s5l8700.h 28791 2010-12-11 09:39:33Z Buschel $
+ *
+ * Copyright (C) 2008 by Marcoen Hirschberg, Bart van Adrichem
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __S5L8702_H__
+#define __S5L8702_H__
+
+#include <inttypes.h>
+
+#define REG8_PTR_T  volatile uint8_t *
+#define REG16_PTR_T volatile uint16_t *
+#define REG32_PTR_T volatile uint32_t *
+
+//TODO: Figure out
+#define TIMER_FREQ  (1843200 * 4 * 26 / 1 / 4) /* 47923200 Hz */
+
+#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+
+/////SYSCON/////
+#define PWRCON(i)    (*((uint32_t volatile*)(0x3C500000 \
+                                           + ((i) == 4 ? 0x6C : \
+                                             ((i) == 3 ? 0x68 : \
+                                             ((i) == 2 ? 0x58 : \
+                                             ((i) == 1 ? 0x4C : \
+                                                         0x48)))))))
+
+
+/////TIMER/////
+#define TACON        (*((uint32_t volatile*)(0x3C700000)))
+#define TACMD        (*((uint32_t volatile*)(0x3C700004)))
+#define TADATA0      (*((uint32_t volatile*)(0x3C700008)))
+#define TADATA1      (*((uint32_t volatile*)(0x3C70000C)))
+#define TAPRE        (*((uint32_t volatile*)(0x3C700010)))
+#define TACNT        (*((uint32_t volatile*)(0x3C700014)))
+#define TBCON        (*((uint32_t volatile*)(0x3C700020)))
+#define TBCMD        (*((uint32_t volatile*)(0x3C700024)))
+#define TBDATA0      (*((uint32_t volatile*)(0x3C700028)))
+#define TBDATA1      (*((uint32_t volatile*)(0x3C70002C)))
+#define TBPRE        (*((uint32_t volatile*)(0x3C700030)))
+#define TBCNT        (*((uint32_t volatile*)(0x3C700034)))
+#define TCCON        (*((uint32_t volatile*)(0x3C700040)))
+#define TCCMD        (*((uint32_t volatile*)(0x3C700044)))
+#define TCDATA0      (*((uint32_t volatile*)(0x3C700048)))
+#define TCDATA1      (*((uint32_t volatile*)(0x3C70004C)))
+#define TCPRE        (*((uint32_t volatile*)(0x3C700050)))
+#define TCCNT        (*((uint32_t volatile*)(0x3C700054)))
+#define TDCON        (*((uint32_t volatile*)(0x3C700060)))
+#define TDCMD        (*((uint32_t volatile*)(0x3C700064)))
+#define TDDATA0      (*((uint32_t volatile*)(0x3C700068)))
+#define TDDATA1      (*((uint32_t volatile*)(0x3C70006C)))
+#define TDPRE        (*((uint32_t volatile*)(0x3C700070)))
+#define TDCNT        (*((uint32_t volatile*)(0x3C700074)))
+#define TECON        (*((uint32_t volatile*)(0x3C7000A0)))
+#define TECMD        (*((uint32_t volatile*)(0x3C7000A4)))
+#define TEDATA0      (*((uint32_t volatile*)(0x3C7000A8)))
+#define TEDATA1      (*((uint32_t volatile*)(0x3C7000AC)))
+#define TEPRE        (*((uint32_t volatile*)(0x3C7000B0)))
+#define TECNT        (*((uint32_t volatile*)(0x3C7000B4)))
+#define TFCON        (*((uint32_t volatile*)(0x3C7000C0)))
+#define TFCMD        (*((uint32_t volatile*)(0x3C7000C4)))
+#define TFDATA0      (*((uint32_t volatile*)(0x3C7000C8)))
+#define TFDATA1      (*((uint32_t volatile*)(0x3C7000CC)))
+#define TFPRE        (*((uint32_t volatile*)(0x3C7000D0)))
+#define TFCNT        (*((uint32_t volatile*)(0x3C7000D4)))
+#define TGCON        (*((uint32_t volatile*)(0x3C7000E0)))
+#define TGCMD        (*((uint32_t volatile*)(0x3C7000E4)))
+#define TGDATA0      (*((uint32_t volatile*)(0x3C7000E8)))
+#define TGDATA1      (*((uint32_t volatile*)(0x3C7000EC)))
+#define TGPRE        (*((uint32_t volatile*)(0x3C7000F0)))
+#define TGCNT        (*((uint32_t volatile*)(0x3C7000F4)))
+#define THCON        (*((uint32_t volatile*)(0x3C700100)))
+#define THCMD        (*((uint32_t volatile*)(0x3C700104)))
+#define THDATA0      (*((uint32_t volatile*)(0x3C700108)))
+#define THDATA1      (*((uint32_t volatile*)(0x3C70010C)))
+#define THPRE        (*((uint32_t volatile*)(0x3C700110)))
+#define THCNT        (*((uint32_t volatile*)(0x3C700114)))
+#define USEC_TIMER   TFCNT
+
+
+/////USB/////
+#define OTGBASE 0x38400000
+#define PHYBASE 0x3C400000
+#define SYNOPSYSOTG_CLOCK 0
+#define SYNOPSYSOTG_AHBCFG 0x2B
+
+
+/////I2C/////
+#define IICCON(bus)  (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
+#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
+#define IICADD(bus)  (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
+#define IICDS(bus)   (*((uint32_t volatile*)(0x3C60000C + 0x300000 * (bus))))
+
+
+/////INTERRUPT CONTROLLERS/////
+#define VICIRQSTATUS(v)       (*((uint32_t volatile*)(0x38E00000 + 0x1000 * (v))))
+#define VICFIQSTATUS(v)       (*((uint32_t volatile*)(0x38E00004 + 0x1000 * (v))))
+#define VICRAWINTR(v)         (*((uint32_t volatile*)(0x38E00008 + 0x1000 * (v))))
+#define VICINTSELECT(v)       (*((uint32_t volatile*)(0x38E0000C + 0x1000 * (v))))
+#define VICINTENABLE(v)       (*((uint32_t volatile*)(0x38E00010 + 0x1000 * (v))))
+#define VICINTENCLEAR(v)      (*((uint32_t volatile*)(0x38E00014 + 0x1000 * (v))))
+#define VICSOFTINT(v)         (*((uint32_t volatile*)(0x38E00018 + 0x1000 * (v))))
+#define VICSOFTINTCLEAR(v)    (*((uint32_t volatile*)(0x38E0001C + 0x1000 * (v))))
+#define VICPROTECTION(v)      (*((uint32_t volatile*)(0x38E00020 + 0x1000 * (v))))
+#define VICSWPRIORITYMASK(v)  (*((uint32_t volatile*)(0x38E00024 + 0x1000 * (v))))
+#define VICPRIORITYDAISY(v)   (*((uint32_t volatile*)(0x38E00028 + 0x1000 * (v))))
+#define VICVECTADDR(v, i)     (*((uint32_t volatile*)(0x38E00100 + 0x1000 * (v) + 4 * (i))))
+#define VICVECTPRIORITY(v, i) (*((uint32_t volatile*)(0x38E00200 + 0x1000 * (v) + 4 * (i))))
+#define VICADDRESS(v)         (*((const void* volatile*)(0x38E00F00 + 0x1000 * (v))))
+#define VIC0IRQSTATUS         (*((uint32_t volatile*)(0x38E00000)))
+#define VIC0FIQSTATUS         (*((uint32_t volatile*)(0x38E00004)))
+#define VIC0RAWINTR           (*((uint32_t volatile*)(0x38E00008)))
+#define VIC0INTSELECT         (*((uint32_t volatile*)(0x38E0000C)))
+#define VIC0INTENABLE         (*((uint32_t volatile*)(0x38E00010)))
+#define VIC0INTENCLEAR        (*((uint32_t volatile*)(0x38E00014)))
+#define VIC0SOFTINT           (*((uint32_t volatile*)(0x38E00018)))
+#define VIC0SOFTINTCLEAR      (*((uint32_t volatile*)(0x38E0001C)))
+#define VIC0PROTECTION        (*((uint32_t volatile*)(0x38E00020)))
+#define VIC0SWPRIORITYMASK    (*((uint32_t volatile*)(0x38E00024)))
+#define VIC0PRIORITYDAISY     (*((uint32_t volatile*)(0x38E00028)))
+#define VIC0VECTADDR(i)       (*((const void* volatile*)(0x38E00100 + 4 * (i))))
+#define VIC0VECTADDR0         (*((const void* volatile*)(0x38E00100)))
+#define VIC0VECTADDR1         (*((const void* volatile*)(0x38E00104)))
+#define VIC0VECTADDR2         (*((const void* volatile*)(0x38E00108)))
+#define VIC0VECTADDR3         (*((const void* volatile*)(0x38E0010C)))
+#define VIC0VECTADDR4         (*((const void* volatile*)(0x38E00110)))
+#define VIC0VECTADDR5         (*((const void* volatile*)(0x38E00114)))
+#define VIC0VECTADDR6         (*((const void* volatile*)(0x38E00118)))
+#define VIC0VECTADDR7         (*((const void* volatile*)(0x38E0011C)))
+#define VIC0VECTADDR8         (*((const void* volatile*)(0x38E00120)))
+#define VIC0VECTADDR9         (*((const void* volatile*)(0x38E00124)))
+#define VIC0VECTADDR10        (*((const void* volatile*)(0x38E00128)))
+#define VIC0VECTADDR11        (*((const void* volatile*)(0x38E0012C)))
+#define VIC0VECTADDR12        (*((const void* volatile*)(0x38E00130)))
+#define VIC0VECTADDR13        (*((const void* volatile*)(0x38E00134)))
+#define VIC0VECTADDR14        (*((const void* volatile*)(0x38E00138)))
+#define VIC0VECTADDR15        (*((const void* volatile*)(0x38E0013C)))
+#define VIC0VECTADDR16        (*((const void* volatile*)(0x38E00140)))
+#define VIC0VECTADDR17        (*((const void* volatile*)(0x38E00144)))
+#define VIC0VECTADDR18        (*((const void* volatile*)(0x38E00148)))
+#define VIC0VECTADDR19        (*((const void* volatile*)(0x38E0014C)))
+#define VIC0VECTADDR20        (*((const void* volatile*)(0x38E00150)))
+#define VIC0VECTADDR21        (*((const void* volatile*)(0x38E00154)))
+#define VIC0VECTADDR22        (*((const void* volatile*)(0x38E00158)))
+#define VIC0VECTADDR23        (*((const void* volatile*)(0x38E0015C)))
+#define VIC0VECTADDR24        (*((const void* volatile*)(0x38E00160)))
+#define VIC0VECTADDR25        (*((const void* volatile*)(0x38E00164)))
+#define VIC0VECTADDR26        (*((const void* volatile*)(0x38E00168)))
+#define VIC0VECTADDR27        (*((const void* volatile*)(0x38E0016C)))
+#define VIC0VECTADDR28        (*((const void* volatile*)(0x38E00170)))
+#define VIC0VECTADDR29        (*((const void* volatile*)(0x38E00174)))
+#define VIC0VECTADDR30        (*((const void* volatile*)(0x38E00178)))
+#define VIC0VECTADDR31        (*((const void* volatile*)(0x38E0017C)))
+#define VIC0VECTPRIORITY(i)   (*((uint32_t volatile*)(0x38E00200 + 4 * (i))))
+#define VIC0VECTPRIORITY0     (*((uint32_t volatile*)(0x38E00200)))
+#define VIC0VECTPRIORITY1     (*((uint32_t volatile*)(0x38E00204)))
+#define VIC0VECTPRIORITY2     (*((uint32_t volatile*)(0x38E00208)))
+#define VIC0VECTPRIORITY3     (*((uint32_t volatile*)(0x38E0020C)))
+#define VIC0VECTPRIORITY4     (*((uint32_t volatile*)(0x38E00210)))
+#define VIC0VECTPRIORITY5     (*((uint32_t volatile*)(0x38E00214)))
+#define VIC0VECTPRIORITY6     (*((uint32_t volatile*)(0x38E00218)))
+#define VIC0VECTPRIORITY7     (*((uint32_t volatile*)(0x38E0021C)))
+#define VIC0VECTPRIORITY8     (*((uint32_t volatile*)(0x38E00220)))
+#define VIC0VECTPRIORITY9     (*((uint32_t volatile*)(0x38E00224)))
+#define VIC0VECTPRIORITY10    (*((uint32_t volatile*)(0x38E00228)))
+#define VIC0VECTPRIORITY11    (*((uint32_t volatile*)(0x38E0022C)))
+#define VIC0VECTPRIORITY12    (*((uint32_t volatile*)(0x38E00230)))
+#define VIC0VECTPRIORITY13    (*((uint32_t volatile*)(0x38E00234)))
+#define VIC0VECTPRIORITY14    (*((uint32_t volatile*)(0x38E00238)))
+#define VIC0VECTPRIORITY15    (*((uint32_t volatile*)(0x38E0023C)))
+#define VIC0VECTPRIORITY16    (*((uint32_t volatile*)(0x38E00240)))
+#define VIC0VECTPRIORITY17    (*((uint32_t volatile*)(0x38E00244)))
+#define VIC0VECTPRIORITY18    (*((uint32_t volatile*)(0x38E00248)))
+#define VIC0VECTPRIORITY19    (*((uint32_t volatile*)(0x38E0024C)))
+#define VIC0VECTPRIORITY20    (*((uint32_t volatile*)(0x38E00250)))
+#define VIC0VECTPRIORITY21    (*((uint32_t volatile*)(0x38E00254)))
+#define VIC0VECTPRIORITY22    (*((uint32_t volatile*)(0x38E00258)))
+#define VIC0VECTPRIORITY23    (*((uint32_t volatile*)(0x38E0025C)))
+#define VIC0VECTPRIORITY24    (*((uint32_t volatile*)(0x38E00260)))
+#define VIC0VECTPRIORITY25    (*((uint32_t volatile*)(0x38E00264)))
+#define VIC0VECTPRIORITY26    (*((uint32_t volatile*)(0x38E00268)))
+#define VIC0VECTPRIORITY27    (*((uint32_t volatile*)(0x38E0026C)))
+#define VIC0VECTPRIORITY28    (*((uint32_t volatile*)(0x38E00270)))
+#define VIC0VECTPRIORITY29    (*((uint32_t volatile*)(0x38E00274)))
+#define VIC0VECTPRIORITY30    (*((uint32_t volatile*)(0x38E00278)))
+#define VIC0VECTPRIORITY31    (*((uint32_t volatile*)(0x38E0027C)))
+#define VIC0ADDRESS           (*((void* volatile*)(0x38E00F00)))
+#define VIC1IRQSTATUS         (*((uint32_t volatile*)(0x38E01000)))
+#define VIC1FIQSTATUS         (*((uint32_t volatile*)(0x38E01004)))
+#define VIC1RAWINTR           (*((uint32_t volatile*)(0x38E01008)))
+#define VIC1INTSELECT         (*((uint32_t volatile*)(0x38E0100C)))
+#define VIC1INTENABLE         (*((uint32_t volatile*)(0x38E01010)))
+#define VIC1INTENCLEAR        (*((uint32_t volatile*)(0x38E01014)))
+#define VIC1SOFTINT           (*((uint32_t volatile*)(0x38E01018)))
+#define VIC1SOFTINTCLEAR      (*((uint32_t volatile*)(0x38E0101C)))
+#define VIC1PROTECTION        (*((uint32_t volatile*)(0x38E01020)))
+#define VIC1SWPRIORITYMASK    (*((uint32_t volatile*)(0x38E01024)))
+#define VIC1PRIORITYDAISY     (*((uint32_t volatile*)(0x38E01028)))
+#define VIC1VECTADDR(i)       (*((const void* volatile*)(0x38E01100 + 4 * (i))))
+#define VIC1VECTADDR0         (*((const void* volatile*)(0x38E01100)))
+#define VIC1VECTADDR1         (*((const void* volatile*)(0x38E01104)))
+#define VIC1VECTADDR2         (*((const void* volatile*)(0x38E01108)))
+#define VIC1VECTADDR3         (*((const void* volatile*)(0x38E0110C)))
+#define VIC1VECTADDR4         (*((const void* volatile*)(0x38E01110)))
+#define VIC1VECTADDR5         (*((const void* volatile*)(0x38E01114)))
+#define VIC1VECTADDR6         (*((const void* volatile*)(0x38E01118)))
+#define VIC1VECTADDR7         (*((const void* volatile*)(0x38E0111C)))
+#define VIC1VECTADDR8         (*((const void* volatile*)(0x38E01120)))
+#define VIC1VECTADDR9         (*((const void* volatile*)(0x38E01124)))
+#define VIC1VECTADDR10        (*((const void* volatile*)(0x38E01128)))
+#define VIC1VECTADDR11        (*((const void* volatile*)(0x38E0112C)))
+#define VIC1VECTADDR12        (*((const void* volatile*)(0x38E01130)))
+#define VIC1VECTADDR13        (*((const void* volatile*)(0x38E01134)))
+#define VIC1VECTADDR14        (*((const void* volatile*)(0x38E01138)))
+#define VIC1VECTADDR15        (*((const void* volatile*)(0x38E0113C)))
+#define VIC1VECTADDR16        (*((const void* volatile*)(0x38E01140)))
+#define VIC1VECTADDR17        (*((const void* volatile*)(0x38E01144)))
+#define VIC1VECTADDR18        (*((const void* volatile*)(0x38E01148)))
+#define VIC1VECTADDR19        (*((const void* volatile*)(0x38E0114C)))
+#define VIC1VECTADDR20        (*((const void* volatile*)(0x38E01150)))
+#define VIC1VECTADDR21        (*((const void* volatile*)(0x38E01154)))
+#define VIC1VECTADDR22        (*((const void* volatile*)(0x38E01158)))
+#define VIC1VECTADDR23        (*((const void* volatile*)(0x38E0115C)))
+#define VIC1VECTADDR24        (*((const void* volatile*)(0x38E01160)))
+#define VIC1VECTADDR25        (*((const void* volatile*)(0x38E01164)))
+#define VIC1VECTADDR26        (*((const void* volatile*)(0x38E01168)))
+#define VIC1VECTADDR27        (*((const void* volatile*)(0x38E0116C)))
+#define VIC1VECTADDR28        (*((const void* volatile*)(0x38E01170)))
+#define VIC1VECTADDR29        (*((const void* volatile*)(0x38E01174)))
+#define VIC1VECTADDR30        (*((const void* volatile*)(0x38E01178)))
+#define VIC1VECTADDR31        (*((const void* volatile*)(0x38E0117C)))
+#define VIC1VECTPRIORITY(i)   (*((uint32_t volatile*)(0x38E01200 + 4 * (i))))
+#define VIC1VECTPRIORITY0     (*((uint32_t volatile*)(0x38E01200)))
+#define VIC1VECTPRIORITY1     (*((uint32_t volatile*)(0x38E01204)))
+#define VIC1VECTPRIORITY2     (*((uint32_t volatile*)(0x38E01208)))
+#define VIC1VECTPRIORITY3     (*((uint32_t volatile*)(0x38E0120C)))
+#define VIC1VECTPRIORITY4     (*((uint32_t volatile*)(0x38E01210)))
+#define VIC1VECTPRIORITY5     (*((uint32_t volatile*)(0x38E01214)))
+#define VIC1VECTPRIORITY6     (*((uint32_t volatile*)(0x38E01218)))
+#define VIC1VECTPRIORITY7     (*((uint32_t volatile*)(0x38E0121C)))
+#define VIC1VECTPRIORITY8     (*((uint32_t volatile*)(0x38E01220)))
+#define VIC1VECTPRIORITY9     (*((uint32_t volatile*)(0x38E01224)))
+#define VIC1VECTPRIORITY10    (*((uint32_t volatile*)(0x38E01228)))
+#define VIC1VECTPRIORITY11    (*((uint32_t volatile*)(0x38E0122C)))
+#define VIC1VECTPRIORITY12    (*((uint32_t volatile*)(0x38E01230)))
+#define VIC1VECTPRIORITY13    (*((uint32_t volatile*)(0x38E01234)))
+#define VIC1VECTPRIORITY14    (*((uint32_t volatile*)(0x38E01238)))
+#define VIC1VECTPRIORITY15    (*((uint32_t volatile*)(0x38E0123C)))
+#define VIC1VECTPRIORITY16    (*((uint32_t volatile*)(0x38E01240)))
+#define VIC1VECTPRIORITY17    (*((uint32_t volatile*)(0x38E01244)))
+#define VIC1VECTPRIORITY18    (*((uint32_t volatile*)(0x38E01248)))
+#define VIC1VECTPRIORITY19    (*((uint32_t volatile*)(0x38E0124C)))
+#define VIC1VECTPRIORITY20    (*((uint32_t volatile*)(0x38E01250)))
+#define VIC1VECTPRIORITY21    (*((uint32_t volatile*)(0x38E01254)))
+#define VIC1VECTPRIORITY22    (*((uint32_t volatile*)(0x38E01258)))
+#define VIC1VECTPRIORITY23    (*((uint32_t volatile*)(0x38E0125C)))
+#define VIC1VECTPRIORITY24    (*((uint32_t volatile*)(0x38E01260)))
+#define VIC1VECTPRIORITY25    (*((uint32_t volatile*)(0x38E01264)))
+#define VIC1VECTPRIORITY26    (*((uint32_t volatile*)(0x38E01268)))
+#define VIC1VECTPRIORITY27    (*((uint32_t volatile*)(0x38E0126C)))
+#define VIC1VECTPRIORITY28    (*((uint32_t volatile*)(0x38E01270)))
+#define VIC1VECTPRIORITY29    (*((uint32_t volatile*)(0x38E01274)))
+#define VIC1VECTPRIORITY30    (*((uint32_t volatile*)(0x38E01278)))
+#define VIC1VECTPRIORITY31    (*((uint32_t volatile*)(0x38E0127C)))
+#define VIC1ADDRESS           (*((void* volatile*)(0x38E01F00)))
+
+
+/////GPIO/////
+#define PCON(i)       (*((uint32_t volatile*)(0x3cf00000 + ((i) << 5))))
+#define PDAT(i)       (*((uint32_t volatile*)(0x3cf00004 + ((i) << 5))))
+#define PUNA(i)       (*((uint32_t volatile*)(0x3cf00008 + ((i) << 5))))
+#define PUNB(i)       (*((uint32_t volatile*)(0x3cf0000c + ((i) << 5))))
+#define PCON0         (*((uint32_t volatile*)(0x3cf00000)))
+#define PDAT0         (*((uint32_t volatile*)(0x3cf00004)))
+#define PCON1         (*((uint32_t volatile*)(0x3cf00020)))
+#define PDAT1         (*((uint32_t volatile*)(0x3cf00024)))
+#define PCON2         (*((uint32_t volatile*)(0x3cf00040)))
+#define PDAT2         (*((uint32_t volatile*)(0x3cf00044)))
+#define PCON3         (*((uint32_t volatile*)(0x3cf00060)))
+#define PDAT3         (*((uint32_t volatile*)(0x3cf00064)))
+#define PCON4         (*((uint32_t volatile*)(0x3cf00080)))
+#define PDAT4         (*((uint32_t volatile*)(0x3cf00084)))
+#define PCON5         (*((uint32_t volatile*)(0x3cf000a0)))
+#define PDAT5         (*((uint32_t volatile*)(0x3cf000a4)))
+#define PCON6         (*((uint32_t volatile*)(0x3cf000c0)))
+#define PDAT6         (*((uint32_t volatile*)(0x3cf000c4)))
+#define PCON7         (*((uint32_t volatile*)(0x3cf000e0)))
+#define PDAT7         (*((uint32_t volatile*)(0x3cf000e4)))
+#define PCON8         (*((uint32_t volatile*)(0x3cf00100)))
+#define PDAT8         (*((uint32_t volatile*)(0x3cf00104)))
+#define PCON9         (*((uint32_t volatile*)(0x3cf00120)))
+#define PDAT9         (*((uint32_t volatile*)(0x3cf00124)))
+#define PCONA         (*((uint32_t volatile*)(0x3cf00140)))
+#define PDATA         (*((uint32_t volatile*)(0x3cf00144)))
+#define PCONB         (*((uint32_t volatile*)(0x3cf00160)))
+#define PDATB         (*((uint32_t volatile*)(0x3cf00164)))
+#define PCONC         (*((uint32_t volatile*)(0x3cf00180)))
+#define PDATC         (*((uint32_t volatile*)(0x3cf00184)))
+#define PCOND         (*((uint32_t volatile*)(0x3cf001a0)))
+#define PDATD         (*((uint32_t volatile*)(0x3cf001a4)))
+#define PCONE         (*((uint32_t volatile*)(0x3cf001c0)))
+#define PDATE         (*((uint32_t volatile*)(0x3cf001c4)))
+#define PCONF         (*((uint32_t volatile*)(0x3cf001e0)))
+#define PDATF         (*((uint32_t volatile*)(0x3cf001e4)))
+#define GPIOCMD       (*((uint32_t volatile*)(0x3cf00200)))
+
+
+/////SPI/////
+#define SPIBASE(i)      ((i) == 2 ? 0x3d200000 : \
+                         (i) == 1 ? 0x3ce00000 : \
+                                    0x3c300000)
+#define SPICLKGATE(i)   ((i) == 2 ? 0x2f : \
+                         (i) == 1 ? 0x2b : \
+                                    0x22)
+#define SPIDMA(i)       ((i) == 2 ? 0xd : \
+                         (i) == 1 ? 0xf : \
+                                    0x5)
+#define SPICTRL(i)    (*((uint32_t volatile*)(SPIBASE(i))))
+#define SPISETUP(i)   (*((uint32_t volatile*)(SPIBASE(i) + 0x4)))
+#define SPISTATUS(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x8)))
+#define SPIUNKREG1(i) (*((uint32_t volatile*)(SPIBASE(i) + 0xc)))
+#define SPITXDATA(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x10)))
+#define SPIRXDATA(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x20)))
+#define SPICLKDIV(i)  (*((uint32_t volatile*)(SPIBASE(i) + 0x30)))
+#define SPIRXLIMIT(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x34)))
+#define SPIUNKREG3(i) (*((uint32_t volatile*)(SPIBASE(i) + 0x38)))
+
+
+/////AES/////
+#define AESCONTROL    (*((uint32_t volatile*)(0x38c00000)))
+#define AESGO         (*((uint32_t volatile*)(0x38c00004)))
+#define AESUNKREG0    (*((uint32_t volatile*)(0x38c00008)))
+#define AESSTATUS     (*((uint32_t volatile*)(0x38c0000c)))
+#define AESUNKREG1    (*((uint32_t volatile*)(0x38c00010)))
+#define AESKEYLEN     (*((uint32_t volatile*)(0x38c00014)))
+#define AESOUTSIZE    (*((uint32_t volatile*)(0x38c00018)))
+#define AESOUTADDR    (*((void* volatile*)(0x38c00020)))
+#define AESINSIZE     (*((uint32_t volatile*)(0x38c00024)))
+#define AESINADDR     (*((const void* volatile*)(0x38c00028)))
+#define AESAUXSIZE    (*((uint32_t volatile*)(0x38c0002c)))
+#define AESAUXADDR    (*((void* volatile*)(0x38c00030)))
+#define AESSIZE3      (*((uint32_t volatile*)(0x38c00034)))
+#define AESKEY          ((uint32_t volatile*)(0x38c0004c))
+#define AESTYPE       (*((uint32_t volatile*)(0x38c0006c)))
+#define AESIV           ((uint32_t volatile*)(0x38c00074))
+#define AESTYPE2      (*((uint32_t volatile*)(0x38c00088)))
+#define AESUNKREG2    (*((uint32_t volatile*)(0x38c0008c)))
+
+
+/////SHA1/////
+#define SHA1CONFIG    (*((uint32_t volatile*)(0x38000000)))
+#define SHA1RESET     (*((uint32_t volatile*)(0x38000004)))
+#define SHA1RESULT      ((uint32_t volatile*)(0x38000020))
+#define SHA1DATAIN      ((uint32_t volatile*)(0x38000040))
+
+
+/////DMA/////
+#ifndef ASM
+struct dma_lli
+{
+    void* srcaddr;
+    void* dstaddr;
+    const struct dma_lli* nextlli;
+    uint32_t control;
+};
+#endif
+#define DMACINTSTS(d)       (*((uint32_t volatile*)(0x38200000 + 0x1700000 * (d))))
+#define DMACINTTCSTS(d)     (*((uint32_t volatile*)(0x38200004 + 0x1700000 * (d))))
+#define DMACINTTCCLR(d)     (*((uint32_t volatile*)(0x38200008 + 0x1700000 * (d))))
+#define DMACINTERRSTS(d)    (*((uint32_t volatile*)(0x3820000c + 0x1700000 * (d))))
+#define DMACINTERRCLR(d)    (*((uint32_t volatile*)(0x38200010 + 0x1700000 * (d))))
+#define DMACRAWINTTCSTS(d)  (*((uint32_t volatile*)(0x38200014 + 0x1700000 * (d))))
+#define DMACRAWINTERRSTS(d) (*((uint32_t volatile*)(0x38200018 + 0x1700000 * (d))))
+#define DMACENABLEDCHANS(d) (*((uint32_t volatile*)(0x3820001c + 0x1700000 * (d))))
+#define DMACSOFTBREQ(d)     (*((uint32_t volatile*)(0x38200020 + 0x1700000 * (d))))
+#define DMACSOFTSREQ(d)     (*((uint32_t volatile*)(0x38200024 + 0x1700000 * (d))))
+#define DMACSOFTLBREQ(d)    (*((uint32_t volatile*)(0x38200028 + 0x1700000 * (d))))
+#define DMACSOFTLSREQ(d)    (*((uint32_t volatile*)(0x3820002c + 0x1700000 * (d))))
+#define DMACCONFIG(d)       (*((uint32_t volatile*)(0x38200030 + 0x1700000 * (d))))
+#define DMACSYNC(d)         (*((uint32_t volatile*)(0x38200034 + 0x1700000 * (d))))
+#define DMACCLLI(d, c)      (*((struct dma_lli volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCSRCADDR(d, c)  (*((const void* volatile*)(0x38200100 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCDESTADDR(d, c) (*((void* volatile*)(0x38200104 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCNEXTLLI(d, c)  (*((const void* volatile*)(0x38200108 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCCONTROL(d, c)  (*((uint32_t volatile*)(0x3820010c + 0x1700000 * (d) + 0x20 * (c))))
+#define DMACCCONFIG(d, c)   (*((uint32_t volatile*)(0x38200110 + 0x1700000 * (d) + 0x20 * (c))))
+#define DMAC0INTSTS         (*((uint32_t volatile*)(0x38200000)))
+#define DMAC0INTTCSTS       (*((uint32_t volatile*)(0x38200004)))
+#define DMAC0INTTCCLR       (*((uint32_t volatile*)(0x38200008)))
+#define DMAC0INTERRSTS      (*((uint32_t volatile*)(0x3820000c)))
+#define DMAC0INTERRCLR      (*((uint32_t volatile*)(0x38200010)))
+#define DMAC0RAWINTTCSTS    (*((uint32_t volatile*)(0x38200014)))
+#define DMAC0RAWINTERRSTS   (*((uint32_t volatile*)(0x38200018)))
+#define DMAC0ENABLEDCHANS   (*((uint32_t volatile*)(0x3820001c)))
+#define DMAC0SOFTBREQ       (*((uint32_t volatile*)(0x38200020)))
+#define DMAC0SOFTSREQ       (*((uint32_t volatile*)(0x38200024)))
+#define DMAC0SOFTLBREQ      (*((uint32_t volatile*)(0x38200028)))
+#define DMAC0SOFTLSREQ      (*((uint32_t volatile*)(0x3820002c)))
+#define DMAC0CONFIG         (*((uint32_t volatile*)(0x38200030)))
+#define DMAC0SYNC           (*((uint32_t volatile*)(0x38200034)))
+#define DMAC0CLLI(c)        (*((struct dma_lli volatile*)(0x38200100 + 0x20 * (c))))
+#define DMAC0CSRCADDR(c)    (*((const void* volatile*)(0x38200100 + 0x20 * (c))))
+#define DMAC0CDESTADDR(c)   (*((void* volatile*)(0x38200104 + 0x20 * (c))))
+#define DMAC0CNEXTLLI(c)    (*((const void* volatile*)(0x38200108 + 0x20 * (c))))
+#define DMAC0CCONTROL(c)    (*((uint32_t volatile*)(0x3820010c + 0x20 * (c))))
+#define DMAC0CCONFIG(c)     (*((uint32_t volatile*)(0x38200110 + 0x20 * (c))))
+#define DMAC0C0LLI          (*((struct dma_lli volatile*)(0x38200100)))
+#define DMAC0C0SRCADDR      (*((const void* volatile*)(0x38200100)))
+#define DMAC0C0DESTADDR     (*((void* volatile*)(0x38200104)))
+#define DMAC0C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200108)))
+#define DMAC0C0CONTROL      (*((uint32_t volatile*)(0x3820010c)))
+#define DMAC0C0CONFIG       (*((uint32_t volatile*)(0x38200110)))
+#define DMAC0C1LLI          (*((struct dma_lli volatile*)(0x38200120)))
+#define DMAC0C1SRCADDR      (*((const void* volatile*)(0x38200120)))
+#define DMAC0C1DESTADDR     (*((void* volatile*)(0x38200124)))
+#define DMAC0C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200128)))
+#define DMAC0C1CONTROL      (*((uint32_t volatile*)(0x3820012c)))
+#define DMAC0C1CONFIG       (*((uint32_t volatile*)(0x38200130)))
+#define DMAC0C2LLI          (*((struct dma_lli volatile*)(0x38200140)))
+#define DMAC0C2SRCADDR      (*((const void* volatile*)(0x38200140)))
+#define DMAC0C2DESTADDR     (*((void* volatile*)(0x38200144)))
+#define DMAC0C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200148)))
+#define DMAC0C2CONTROL      (*((uint32_t volatile*)(0x3820014c)))
+#define DMAC0C2CONFIG       (*((uint32_t volatile*)(0x38200150)))
+#define DMAC0C3LLI          (*((struct dma_lli volatile*)(0x38200160)))
+#define DMAC0C3SRCADDR      (*((const void* volatile*)(0x38200160)))
+#define DMAC0C3DESTADDR     (*((void* volatile*)(0x38200164)))
+#define DMAC0C3NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200168)))
+#define DMAC0C3CONTROL      (*((uint32_t volatile*)(0x3820016c)))
+#define DMAC0C3CONFIG       (*((uint32_t volatile*)(0x38200170)))
+#define DMAC0C4LLI          (*((struct dma_lli volatile*)(0x38200180)))
+#define DMAC0C4SRCADDR      (*((const void* volatile*)(0x38200180)))
+#define DMAC0C4DESTADDR     (*((void* volatile*)(0x38200184)))
+#define DMAC0C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x38200188)))
+#define DMAC0C4CONTROL      (*((uint32_t volatile*)(0x3820018c)))
+#define DMAC0C4CONFIG       (*((uint32_t volatile*)(0x38200190)))
+#define DMAC0C5LLI          (*((struct dma_lli volatile*)(0x382001a0)))
+#define DMAC0C5SRCADDR      (*((const void* volatile*)(0x382001a0)))
+#define DMAC0C5DESTADDR     (*((void* volatile*)(0x382001a4)))
+#define DMAC0C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001a8)))
+#define DMAC0C5CONTROL      (*((uint32_t volatile*)(0x382001ac)))
+#define DMAC0C5CONFIG       (*((uint32_t volatile*)(0x382001b0)))
+#define DMAC0C6LLI          (*((struct dma_lli volatile*)(0x382001c0)))
+#define DMAC0C6SRCADDR      (*((const void* volatile*)(0x382001c0)))
+#define DMAC0C6DESTADDR     (*((void* volatile*)(0x382001c4)))
+#define DMAC0C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001c8)))
+#define DMAC0C6CONTROL      (*((uint32_t volatile*)(0x382001cc)))
+#define DMAC0C6CONFIG       (*((uint32_t volatile*)(0x382001d0)))
+#define DMAC0C7LLI          (*((struct dma_lli volatile*)(0x382001e0)))
+#define DMAC0C7SRCADDR      (*((const void* volatile*)(0x382001e0)))
+#define DMAC0C7DESTADDR     (*((void* volatile*)(0x382001e4)))
+#define DMAC0C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x382001e8)))
+#define DMAC0C7CONTROL      (*((uint32_t volatile*)(0x382001ec)))
+#define DMAC0C7CONFIG       (*((uint32_t volatile*)(0x382001f0)))
+#define DMAC1INTSTS         (*((uint32_t volatile*)(0x39900000)))
+#define DMAC1INTTCSTS       (*((uint32_t volatile*)(0x39900004)))
+#define DMAC1INTTCCLR       (*((uint32_t volatile*)(0x39900008)))
+#define DMAC1INTERRSTS      (*((uint32_t volatile*)(0x3990000c)))
+#define DMAC1INTERRCLR      (*((uint32_t volatile*)(0x39900010)))
+#define DMAC1RAWINTTCSTS    (*((uint32_t volatile*)(0x39900014)))
+#define DMAC1RAWINTERRSTS   (*((uint32_t volatile*)(0x39900018)))
+#define DMAC1ENABLEDCHANS   (*((uint32_t volatile*)(0x3990001c)))
+#define DMAC1SOFTBREQ       (*((uint32_t volatile*)(0x39900020)))
+#define DMAC1SOFTSREQ       (*((uint32_t volatile*)(0x39900024)))
+#define DMAC1SOFTLBREQ      (*((uint32_t volatile*)(0x39900028)))
+#define DMAC1SOFTLSREQ      (*((uint32_t volatile*)(0x3990002c)))
+#define DMAC1CONFIG         (*((uint32_t volatile*)(0x39900030)))
+#define DMAC1SYNC           (*((uint32_t volatile*)(0x39900034)))
+#define DMAC1CLLI(c)        (*((struct dma_lli volatile*)(0x39900100 + 0x20 * (c))))
+#define DMAC1CSRCADDR(c)    (*((const void* volatile*)(0x39900100 + 0x20 * (c))))
+#define DMAC1CDESTADDR(c)   (*((void* volatile*)(0x39900104 + 0x20 * (c))))
+#define DMAC1CNEXTLLI(c)    (*((const void* volatile*)(0x39900108 + 0x20 * (c))))
+#define DMAC1CCONTROL(c)    (*((uint32_t volatile*)(0x3990010c + 0x20 * (c))))
+#define DMAC1CCONFIG(c)     (*((uint32_t volatile*)(0x39900110 + 0x20 * (c))))
+#define DMAC1C0LLI          (*((struct dma_lli volatile*)(0x39900100)))
+#define DMAC1C0SRCADDR      (*((const void* volatile*)(0x39900100)))
+#define DMAC1C0DESTADDR     (*((void* volatile*)(0x39900104)))
+#define DMAC1C0NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900108)))
+#define DMAC1C0CONTROL      (*((uint32_t volatile*)(0x3990010c)))
+#define DMAC1C0CONFIG       (*((uint32_t volatile*)(0x39900110)))
+#define DMAC1C1LLI          (*((struct dma_lli volatile*)(0x39900120)))
+#define DMAC1C1SRCADDR      (*((const void* volatile*)(0x39900120)))
+#define DMAC1C1DESTADDR     (*((void* volatile*)(0x39900124)))
+#define DMAC1C1NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900128)))
+#define DMAC1C1CONTROL      (*((uint32_t volatile*)(0x3990012c)))
+#define DMAC1C1CONFIG       (*((uint32_t volatile*)(0x39900130)))
+#define DMAC1C2LLI          (*((struct dma_lli volatile*)(0x39900140)))
+#define DMAC1C2SRCADDR      (*((const void* volatile*)(0x39900140)))
+#define DMAC1C2DESTADDR     (*((void* volatile*)(0x39900144)))
+#define DMAC1C2NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900148)))
+#define DMAC1C2CONTROL      (*((uint32_t volatile*)(0x3990014c)))
+#define DMAC1C2CONFIG       (*((uint32_t volatile*)(0x39900150)))
+#define DMAC1C3LLI          (*((struct dma_lli volatile*)(0x39900160)))
+#define DMAC1C3SRCADDR      (*((const void* volatile*)(0x39900160)))
+#define DMAC1C3DESTADDR     (*((void* volatile*)(0x39900164)))
+#define DMAC1C3NEXTLLI      (*((volatile void**)(0x39900168)))
+#define DMAC1C3CONTROL      (*((uint32_t volatile*)(0x3990016c)))
+#define DMAC1C3CONFIG       (*((uint32_t volatile*)(0x39900170)))
+#define DMAC1C4LLI          (*((struct dma_lli volatile*)(0x39900180)))
+#define DMAC1C4SRCADDR      (*((const void* volatile*)(0x39900180)))
+#define DMAC1C4DESTADDR     (*((void* volatile*)(0x39900184)))
+#define DMAC1C4NEXTLLI      (*((const struct dma_lli* volatile*)(0x39900188)))
+#define DMAC1C4CONTROL      (*((uint32_t volatile*)(0x3990018c)))
+#define DMAC1C4CONFIG       (*((uint32_t volatile*)(0x39900190)))
+#define DMAC1C5LLI          (*((struct dma_lli volatile*)(0x399001a0)))
+#define DMAC1C5SRCADDR      (*((const void* volatile*)(0x399001a0)))
+#define DMAC1C5DESTADDR     (*((void* volatile*)(0x399001a4)))
+#define DMAC1C5NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001a8)))
+#define DMAC1C5CONTROL      (*((uint32_t volatile*)(0x399001ac)))
+#define DMAC1C5CONFIG       (*((uint32_t volatile*)(0x399001b0)))
+#define DMAC1C6LLI          (*((struct dma_lli volatile*)(0x399001c0)))
+#define DMAC1C6SRCADDR      (*((const void* volatile*)(0x399001c0)))
+#define DMAC1C6DESTADDR     (*((void* volatile*)(0x399001c4)))
+#define DMAC1C6NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001c8)))
+#define DMAC1C6CONTROL      (*((uint32_t volatile*)(0x399001cc)))
+#define DMAC1C6CONFIG       (*((uint32_t volatile*)(0x399001d0)))
+#define DMAC1C7LLI          (*((struct dma_lli volatile*)(0x399001e0)))
+#define DMAC1C7SRCADDR      (*((const void* volatile*)(0x399001e0)))
+#define DMAC1C7DESTADDR     (*((void* volatile*)(0x399001e4)))
+#define DMAC1C7NEXTLLI      (*((const struct dma_lli* volatile*)(0x399001e8)))
+#define DMAC1C7CONTROL      (*((uint32_t volatile*)(0x399001ec)))
+#define DMAC1C7CONFIG       (*((uint32_t volatile*)(0x399001f0)))
+
+
+/////LCD/////
+#define LCDWCMD   (*((uint32_t volatile*)(0x38300004)))
+#define LCDSTATUS (*((uint32_t volatile*)(0x3830001c)))
+#define LCDWDATA  (*((uint32_t volatile*)(0x38300040)))
+
+
+/////ATA/////
+#define ATA_CCONTROL        (*((uint32_t volatile*)(0x38700000)))
+#define ATA_CSTATUS         (*((uint32_t volatile*)(0x38700004)))
+#define ATA_CCOMMAND        (*((uint32_t volatile*)(0x38700008)))
+#define ATA_SWRST           (*((uint32_t volatile*)(0x3870000c)))
+#define ATA_IRQ             (*((uint32_t volatile*)(0x38700010)))
+#define ATA_IRQ_MASK        (*((uint32_t volatile*)(0x38700014)))
+#define ATA_CFG             (*((uint32_t volatile*)(0x38700018)))
+#define ATA_MDMA_TIME       (*((uint32_t volatile*)(0x38700028)))
+#define ATA_PIO_TIME        (*((uint32_t volatile*)(0x3870002c)))
+#define ATA_UDMA_TIME       (*((uint32_t volatile*)(0x38700030)))
+#define ATA_XFR_NUM         (*((uint32_t volatile*)(0x38700034)))
+#define ATA_XFR_CNT         (*((uint32_t volatile*)(0x38700038)))
+#define ATA_TBUF_START      (*((void* volatile*)(0x3870003c)))
+#define ATA_TBUF_SIZE       (*((uint32_t volatile*)(0x38700040)))
+#define ATA_SBUF_START      (*((void* volatile*)(0x38700044)))
+#define ATA_SBUF_SIZE       (*((uint32_t volatile*)(0x38700048)))
+#define ATA_CADR_TBUF       (*((void* volatile*)(0x3870004c)))
+#define ATA_CADR_SBUF       (*((void* volatile*)(0x38700050)))
+#define ATA_DATA            (*((uint32_t volatile*)(0x38700054)))
+#define ATA_ERROR           (*((uint32_t volatile*)(0x38700058)))
+#define ATA_NSECTOR         (*((uint32_t volatile*)(0x3870005c)))
+#define ATA_SECTOR          (*((uint32_t volatile*)(0x38700060)))
+#define ATA_LCYL            (*((uint32_t volatile*)(0x38700064)))
+#define ATA_HCYL            (*((uint32_t volatile*)(0x38700068)))
+#define ATA_SELECT          (*((uint32_t volatile*)(0x3870006c)))
+#define ATA_COMMAND         (*((uint32_t volatile*)(0x38700070)))
+#define ATA_CONTROL         (*((uint32_t volatile*)(0x38700074)))
+#define ATA_PIO_READY       (*((uint32_t volatile*)(0x38700078)))
+#define ATA_PIO_RDATA       (*((uint32_t volatile*)(0x3870007c)))
+#define ATA_BUS_FIFO_STATUS (*((uint32_t volatile*)(0x38700080)))
+#define ATA_FIFO_STATUS     (*((uint32_t volatile*)(0x38700084)))
+#define ATA_DMA_ADDR        (*((void* volatile*)(0x38700088)))
+
+
+/////CLICKWHEEL/////
+#define WHEEL00      (*((uint32_t volatile*)(0x3C200000)))
+#define WHEEL04      (*((uint32_t volatile*)(0x3C200004)))
+#define WHEEL08      (*((uint32_t volatile*)(0x3C200008)))
+#define WHEEL0C      (*((uint32_t volatile*)(0x3C20000C)))
+#define WHEEL10      (*((uint32_t volatile*)(0x3C200010)))
+#define WHEELINT     (*((uint32_t volatile*)(0x3C200014)))
+#define WHEELRX      (*((uint32_t volatile*)(0x3C200018)))
+#define WHEELTX      (*((uint32_t volatile*)(0x3C20001C)))
+
+
+/////CLOCK GATES/////
+#define CLOCKGATE_USB_1 2
+#define CLOCKGATE_USB_2 35
+
+
+/////INTERRUPTS/////
+#define IRQ_TIMER 8
+#define IRQ_USB_FUNC 19
+#define IRQ_DMAC(d) 16 + d
+#define IRQ_DMAC0 16
+#define IRQ_DMAC1 17
+#define IRQ_WHEEL 23
+#define IRQ_ATA 29
+
+
+#endif
Index: firmware/SOURCES
===================================================================
--- firmware/SOURCES	(revision 28885)
+++ firmware/SOURCES	(working copy)
@@ -455,6 +455,8 @@
 /* no i2c driver yet */
 #elif CONFIG_I2C == I2C_S5L8700
 target/arm/s5l8700/i2c-s5l8700.c
+#elif CONFIG_I2C == I2C_S5L8702
+target/arm/s5l8702/i2c-s5l8702.c
 #endif
 
 #if CONFIG_CPU == PNX0101
@@ -525,8 +527,10 @@
 target/arm/tcc780x/crt0.S
 #elif CONFIG_CPU==IMX31L
 target/arm/imx31/crt0.S
-#elif defined(CPU_S5L870X)
+#elif CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
 target/arm/s5l8700/crt0.S
+#elif CONFIG_CPU==S5L8702
+target/arm/s5l8702/crt0.S
 #elif defined(CPU_ARM)
 target/arm/crt0.S
 #endif /* defined(CPU_*) */
@@ -1439,13 +1443,7 @@
 #endif /* COWON_D2 */
 
 #ifdef CPU_S5L870X
-target/arm/s5l8700/system-s5l8700.c
 target/arm/mmu-arm.S
-#ifndef SIMULATOR
-#ifndef BOOTLOADER
-target/arm/s5l8700/timer-s5l8700.c
-#endif /* BOOTLOADER */
-#endif /* SIMULATOR */
 #endif
 
 #ifdef MEIZU_M6SL
@@ -1502,6 +1500,7 @@
 target/arm/s5l8700/postmortemstub.S
 target/arm/s5l8700/kernel-s5l8700.c
 target/arm/s5l8700/dma-s5l8700.c
+target/arm/s5l8700/system-s5l8700.c
 target/arm/s5l8700/ipodnano2g/backlight-nano2g.c
 target/arm/s5l8700/ipodnano2g/lcd-nano2g.c
 target/arm/s5l8700/ipodnano2g/lcd-asm-nano2g.S
@@ -1513,6 +1512,7 @@
 target/arm/s5l8700/ipodnano2g/rtc-nano2g.c
 #ifndef BOOTLOADER
 target/arm/usb-s3c6400x.c
+target/arm/s5l8700/timer-s5l8700.c
 target/arm/s5l8700/debug-s5l8700.c
 target/arm/s5l8700/pcm-s5l8700.c
 target/arm/s5l8700/wmcodec-s5l8700.c
@@ -1522,7 +1522,37 @@
 #endif
 #endif
 
+#ifdef IPOD_6G
 #ifndef SIMULATOR
+target/arm/ipod/button-clickwheel.c
+target/arm/s5l8702/ipod6g/backlight-ipod6g.c
+target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c
+target/arm/s5l8702/ipod6g/power-ipod6g.c
+#if 0 //TODO
+target/arm/s5l8702/ipod6g/ata-ipod6g.c
+target/arm/s5l8702/postmortemstub.S
+target/arm/s5l8702/kernel-s5l8702.c
+target/arm/s5l8702/dma-s5l8702.c
+target/arm/s5l8702/system-s5l8702.c
+target/arm/s5l8702/ipod6g/lcd-ipod6g.c
+#endif
+target/arm/s5l8702/ipod6g/pmu-ipod6g.c
+target/arm/s5l8702/ipod6g/rtc-ipod6g.c
+#ifndef BOOTLOADER
+target/arm/usb-s3c6400x.c
+#if 0 //TODO
+target/arm/s5l8702/timer-s5l8702.c
+target/arm/s5l8702/debug-s5l8702.c
+target/arm/s5l8702/pcm-s5l8702.c
+target/arm/s5l8702/wmcodec-s5l8702.c
+target/arm/s5l8702/ipod6g/audio-ipod6g.c
+#endif
+target/arm/s5l8702/ipod6g/adc-ipod6g.c
+#endif
+#endif
+#endif
+
+#ifndef SIMULATOR
 #if CONFIG_CPU == JZ4732
 target/mips/ingenic_jz47xx/ata-nand-jz4740.c
 target/mips/ingenic_jz47xx/ata-sd-jz4740.c
Index: firmware/target/arm/mmu-arm.S
===================================================================
--- firmware/target/arm/mmu-arm.S	(revision 28885)
+++ firmware/target/arm/mmu-arm.S	(working copy)
@@ -18,6 +18,7 @@
  * KIND, either express or implied.
  *
  ****************************************************************************/
+#define ASM
 #include "config.h"
 #include "cpu.h"
 
@@ -27,7 +28,7 @@
 /* MMU present but unused */
 #define HAVE_TEST_AND_CLEAN_CACHE
 
-#elif CONFIG_CPU == DM320 || CONFIG_CPU == AS3525v2
+#elif CONFIG_CPU == DM320 || CONFIG_CPU == AS3525v2 || CONFIG_CPU == S5L8702
 #define USE_MMU
 #define HAVE_TEST_AND_CLEAN_CACHE
 
Index: firmware/target/arm/s5l8700/ipodnano2g/piezo-nano2g.c
===================================================================
--- firmware/target/arm/s5l8700/ipodnano2g/piezo-nano2g.c	(revision 0)
+++ firmware/target/arm/s5l8700/ipodnano2g/piezo-nano2g.c	(revision 0)
@@ -0,0 +1,95 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006-2007 Robert Keevil
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "system.h"
+#include "kernel.h"
+#include "piezo.h"
+
+static unsigned int duration;
+static bool beeping;
+
+void INT_TIMERD(void)
+{
+    /* clear interrupt */
+    TDCON = TDCON;
+    if (!(--duration))
+    {
+        beeping = 0;
+        TDCMD = (1 << 1);   /* TD_CLR */
+    }
+}
+
+void piezo_start(unsigned short cycles, unsigned short periods)
+{
+#ifndef SIMULATOR
+    duration = periods;
+    beeping = 1;
+    /* configure timer for 100 kHz */
+    TDCMD = (1 << 1);   /* TD_CLR */
+    TDPRE = 30 - 1;    /* prescaler */
+    TDCON = (1 << 13) | /* TD_INT1_EN */
+            (0 << 12) | /* TD_INT0_EN */
+            (0 << 11) | /* TD_START */
+            (2 << 8) |  /* TD_CS = PCLK / 16 */
+            (1 << 4);   /* TD_MODE_SEL = PWM mode */
+    TDDATA0 = cycles;   /* set interval period */
+    TDDATA1 = cycles << 1; /* set interval period */
+    TDCMD = (1 << 0);   /* TD_EN */
+
+    /* enable timer interrupt */
+    INTMSK |= INTMSK_TIMERD;
+#endif
+}
+
+void piezo_stop(void)
+{
+#ifndef SIMULATOR
+    TDCMD = (1 << 1);   /* TD_CLR */
+#endif
+}
+
+void piezo_clear(void)
+{
+    piezo_stop();
+}
+
+bool piezo_busy(void)
+{
+    return beeping;
+}
+
+void piezo_init(void)
+{
+    beeping = 0;
+}
+
+void piezo_button_beep(bool beep, bool force)
+{
+    if (force)
+        while (beeping)
+            yield();
+
+    if (!beeping)
+    {
+        if (beep)
+            piezo_start(22, 457);
+        else
+            piezo_start(40, 4);
+    }
+}
Index: firmware/target/arm/s5l8700/ipodnano2g/piezo.h
===================================================================
--- firmware/target/arm/s5l8700/ipodnano2g/piezo.h	(revision 0)
+++ firmware/target/arm/s5l8700/ipodnano2g/piezo.h	(revision 0)
@@ -0,0 +1,24 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id$
+ *
+ * Copyright (C) 2006-2007 Robert Keevil
+ *
+ * All files in this archive are subject to the GNU General Public License.
+ * See the file COPYING in the source tree root for full license agreement.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+void piezo_init(void);
+void piezo_stop(void);
+void piezo_clear(void);
+bool piezo_busy(void);
+void piezo_button_beep(bool beep, bool force);
Index: firmware/target/arm/s5l8702/app.lds
===================================================================
--- firmware/target/arm/s5l8702/app.lds	(revision 0)
+++ firmware/target/arm/s5l8702/app.lds	(revision 0)
@@ -0,0 +1,144 @@
+#define ASM
+#include "config.h"
+#include "cpu.h"
+
+ENTRY(start)
+
+OUTPUT_FORMAT(elf32-littlearm)
+OUTPUT_ARCH(arm)
+STARTUP(target/arm/s5l8702/crt0.o)
+
+#define PLUGINSIZE PLUGIN_BUFFER_SIZE
+#define CODECSIZE CODEC_SIZE
+
+#define IRAMORIG 0x0
+#define DRAMORIG 0x08000000
+
+/* End of the audio buffer, where the codec buffer starts */
+#define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE)
+
+#define DRAM_SIZE (MEMORYSIZE * 0x100000)
+
+#define DRAMSIZE (DRAM_SIZE - PLUGINSIZE - CODECSIZE)
+#define CODECORIG (ENDAUDIOADDR)
+#define IRAMSIZE (48*1024)  /* 256KB total - 48KB for core, 208KB for plugins */
+
+/* Where the codec buffer ends, and the plugin buffer starts */
+#define ENDADDR (ENDAUDIOADDR + CODECSIZE)
+
+MEMORY
+{
+    IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+    DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+}
+
+SECTIONS
+{
+    loadaddress = DRAMORIG;
+
+    .intvect : {
+        _intvectstart = . ;
+        *(.intvect)
+        _intvectend = _newstart ;  
+    } >IRAM AT> DRAM
+    _intvectcopy = LOADADDR(.intvect) ;
+
+    .text :
+    {
+        _loadaddress = .;
+        _textstart = .;
+        *(.init.text)
+        *(.text)
+        *(.text*)
+        *(.glue_7)
+        *(.glue_7t)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .rodata :
+    {
+        *(.rodata*)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    .data :
+    {
+        *(.data*)
+        . = ALIGN(0x4);
+    } > DRAM
+
+    /DISCARD/ :
+    {
+        *(.eh_frame)
+    }
+
+    .iram :
+    {
+        _iramstart = .;
+        *(.icode)
+        *(.irodata)
+        *(.idata)
+        . = ALIGN(0x4);
+        _iramend = .;
+    } > IRAM AT> DRAM
+    _iramcopy = LOADADDR(.iram) ;
+
+    .ibss (NOLOAD) :
+    {
+        _iedata = .;
+        *(.qharray)
+        *(.ibss)
+        . = ALIGN(0x4);
+        _iend = .;
+    } > IRAM
+
+    .stack (NOLOAD) :
+    {
+       *(.stack)
+       stackbegin = .;
+       _stackbegin = .;
+       . += 0x4000;
+       stackend = .;
+       _stackend = .;
+       _irqstackbegin = .;
+       . += 0x400;
+       _irqstackend = .;
+       _fiqstackbegin = .;
+       . += 0x400;
+       _fiqstackend = .;
+    } > IRAM
+
+    .bss (NOLOAD) :
+    {
+       _edata = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(0x4);
+       _end = .;
+    } > DRAM
+
+    .audiobuf (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _audiobuffer = .;
+        audiobuffer = .;
+    } > DRAM
+
+    .audiobufend ENDAUDIOADDR (NOLOAD) :
+    {
+        audiobufend = .;
+        _audiobufend = .;
+    } > DRAM
+
+    .codec CODECORIG (NOLOAD) :
+    {
+        codecbuf = .;
+        _codecbuf = .;
+    } > DRAM
+
+    .plugin ENDADDR (NOLOAD) :
+    {
+        _pluginbuf = .;
+        pluginbuf = .;
+    }
+}
Index: firmware/target/arm/s5l8702/boot.lds
===================================================================
--- firmware/target/arm/s5l8702/boot.lds	(revision 0)
+++ firmware/target/arm/s5l8702/boot.lds	(revision 0)
@@ -0,0 +1,94 @@
+#define ASM
+#include "config.h"
+
+ENTRY(start)
+#ifdef ROCKBOX_LITTLE_ENDIAN
+OUTPUT_FORMAT(elf32-littlearm)
+#else
+OUTPUT_FORMAT(elf32-bigarm)
+#endif
+OUTPUT_ARCH(arm)
+STARTUP(target/arm/s5l8702/crt0.o)
+
+#ifdef IPOD_NANO2G
+#define DRAMORIG 0x08000000 + ((MEMORYSIZE - 1) * 0x100000)
+#define DRAMSIZE 0x00100000
+#else
+#define DRAMORIG 0x08000000
+#define DRAMSIZE (MEMORYSIZE * 0x100000)
+#endif
+
+#define IRAMORIG 0x22000000
+#define IRAMSIZE 256K
+
+MEMORY
+{
+    DRAM  : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
+    IRAM  : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
+}
+
+#define LOAD_AREA IRAM
+
+SECTIONS
+{
+#ifdef NEEDS_INTVECT_COPYING
+  .intvect : {
+    _intvectstart = . ;
+    *(.intvect)
+    _intvectend = _newstart ;  
+  } >IRAM AT> LOAD_AREA
+  _intvectcopy = LOADADDR(.intvect) ;
+#endif
+
+  .text : {
+#ifndef NEEDS_INTVECT_COPYING
+    *(.intvect)
+#endif
+    *(.init.text)
+    *(.text*)
+    *(.glue_7*)
+  } > LOAD_AREA
+
+  .rodata : {
+    *(.rodata*)
+    . = ALIGN(0x4);
+  } > LOAD_AREA
+
+  .data : {
+    _datastart = . ;
+    *(.irodata)
+    *(.icode)
+    *(.idata)
+    *(.data*)
+    *(.ncdata*);
+    . = ALIGN(0x4);
+    _dataend = . ;
+   } > IRAM AT> LOAD_AREA
+   _datacopy = LOADADDR(.data) ;
+
+  .stack (NOLOAD) :
+  {
+     *(.stack)
+     _stackbegin = .;
+     stackbegin = .;
+     . += 0x2000;
+     _stackend = .;
+     stackend = .;
+     _irqstackbegin = .;
+     . += 0x400;
+     _irqstackend = .;
+     _fiqstackbegin = .;
+     . += 0x400;
+     _fiqstackend = .;
+  } > IRAM
+
+  .bss (NOLOAD) : {
+     _edata = .;
+     *(.bss*);
+     *(.ibss);
+     *(.ncbss*);
+     *(COMMON);
+    . = ALIGN(0x4);
+     _end = .;
+  } > IRAM
+}
Index: firmware/target/arm/s5l8702/crt0.S
===================================================================
--- firmware/target/arm/s5l8702/crt0.S	(revision 0)
+++ firmware/target/arm/s5l8702/crt0.S	(revision 0)
@@ -0,0 +1,536 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: crt0.S 18776 2008-10-11 18:32:17Z gevaerts $
+ *
+ * Copyright (C) 2008 by Marcoen Hirschberg
+ * Copyright (C) 2008 by Denes Balatoni
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#define ASM
+#include "config.h"
+#include "cpu.h"
+
+/* Meizu M3 SDRAM settings */
+#ifdef MEIZU_M3
+#define SDR_DSS_SEL_B   1
+#define SDR_DSS_SEL_O   1
+#define SDR_DSS_SEL_C   1
+#define SDR_TIMING      0x6A491D
+#define SDR_CONFIG      0x900
+#define SDR_MRS         0x37
+#define SDR_EMRS        0x4000
+#endif
+
+/* Meizu M6SP SDRAM settings */
+#ifdef MEIZU_M6SP
+#define SDR_DSS_SEL_B   5
+#define SDR_DSS_SEL_O   2
+#define SDR_DSS_SEL_C   2
+#define SDR_TIMING      0x6A4965
+#define SDR_CONFIG      0x700
+#define SDR_MRS         0x33
+#define SDR_EMRS        0x4033
+#endif
+
+    .section .intvect,"ax",%progbits
+    .global    start
+    .global    _newstart
+    /* Exception vectors */
+start:
+    b _newstart
+    ldr pc, =undef_instr_handler
+    ldr pc, =software_int_handler
+    ldr pc, =prefetch_abort_handler
+    ldr pc, =data_abort_handler
+    ldr pc, =reserved_handler
+    ldr pc, =irq_handler
+    ldr pc, =fiq_handler
+#if CONFIG_CPU==S5L8700
+    .word 0x43554644 /* DFUC */
+#endif
+    .ltorg
+_newstart:
+#if CONFIG_CPU!=S5L8701 || !defined(BOOTLOADER)
+    ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
+    .section .init.text,"ax",%progbits
+newstart2:
+#endif
+    msr     cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */
+
+#ifdef ROCKBOX_BIG_ENDIAN
+    mov r1, #0x80
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // set bigendian
+#endif
+
+    ldr r1, =0x3c800000 // disable watchdog
+    mov r0, #0xa5
+    str r0, [r1]
+
+    mov r0, #0
+    mov r1, #0x39c00000
+    str r0, [r1,#0x08] // mask all interrupts
+    str r0, [r1,#0x20] // mask all external interrupts
+    mvn r0, #0
+    str r0, [r1,#0x1c] // clear pending external interrupts
+    str r0, [r1] // irq priority
+    str r0, [r1,#0x10] // clear pending interrupts
+
+//    ldr r1, =0x3cf00000
+//    ldr r0, [r1]
+//    mvn r2, #0x30
+//    and r0, r0, r2
+//    mov r2, #0x10
+//    orr r0, r0, r2
+//    str r0, [r1]
+//    ldr r0, [r1,#0x04]
+//    mov r2, #4
+//    orr r0, r0, r2
+//    str r0, [r1,#0x04] // switch backlight on
+
+#if CONFIG_CPU==S5L8701
+    ldr r1, =0x38200000
+    ldr r2, [r1]
+    orr r2, r2, #1
+    bic r2, r2, #0x10000
+    str r2, [r1] // remap iram to address 0x0
+
+#ifdef BOOTLOADER
+    /* Relocate ourself to IRAM - we have been loaded to DRAM */
+    mov    r0, #0x08000000   /* source (DRAM) */
+    mov    r1, #0x22000000   /* dest (IRAM) */
+    ldr    r2, =_dataend
+1:
+    cmp    r2, r1
+    ldrhi  r3, [r0], #4
+    strhi  r3, [r1], #4
+    bhi    1b
+
+    ldr    pc, =start_loc    /* jump to the relocated start_loc:  */
+start_loc:
+#endif /* BOOTLOADER */
+#endif /* CONFIG_CPU==S5L8701 */
+
+#if !(CONFIG_CPU==S5L8701 && defined(BOOTLOADER))
+    ldr r1, =0x3c500000 
+    ldr r0, =0x00800080
+    str r0, [r1]        // CLKCON
+    mov r0, #0
+    str r0, [r1,#0x24]  // PLLCON
+#ifdef IPOD_NANO2G
+    ldr r0, =0x021200   // pdiv=2, mdiv=0x12 sdiv=0, 192 MHz
+#else
+    ldr r0, =0x1ad200   // pdiv=0x1a, mdiv=0xd2 sdiv=0
+#endif
+    str r0, [r1,#0x04]  // PLL0PMS
+    mov r0, #0
+    str r0, [r1,#0x08]  // PLL1PMS
+    ldr r0, =280
+    str r0, [r1,#0x14]  // PLL0LCNT
+    mov r0, #3
+    str r0, [r1,#0x24]  // PLLCON
+1:
+    ldr r0, [r1,#0x20]  // PLLLOCK
+    tst r0, #1
+    beq 1b
+    mov r0, #0x280
+    str r0, [r1,#0x3c]  // CLKCON2
+    ldr r0, =0x20803180 // FCLK_CPU = 200MHz, HCLK = 100MHz, PCLK = 50MHz, other clocks off
+    str r0, [r1]        // CLKCON
+    mov r0, #0x37       // SCLK = 25MHz
+    str r0, [r1,#0x10]  // CLKCON3
+
+    ldr r2, =0xc0000078
+    mrc 15, 0, r0, c1, c0, 0
+    mvn r1, #0xc0000000
+    and r0, r0, r1
+    orr r0, r0, r2
+    mcr 15, 0, r0, c1, c0, 0 // asynchronous clocking mode
+    nop
+    nop                         
+    nop
+    nop
+#endif
+
+//    ldr r0, =0x10100000
+//    ldr r1, =0x38200034
+//    str r0, [r1] // SRAM0/1 data width 16 bit
+//    ldr r0, =0x00220922
+//    ldr r7, =0x38200038
+//    str r0, [r7] // SRAM0/1 clocks
+//    ldr r0, =0x00220922
+//    ldr r9, =0x3820003c
+//    str r0, [r9] // SRAM2/3 clocks
+//    nop
+//    nop
+//    nop
+//    nop
+
+/* The following two sections of code (i.e. Nano2G and Meizus) should
+   be unified at some point. */
+#ifdef IPOD_NANO2G
+
+    ldr r1, =0x3c500000 
+    ldr r0, =0xffdff7ff
+    str r0, [r1,#0x28]  // PWRCON
+    ldr r0, =0xffffef7e
+    str r0, [r1,#0x40]  // PWRCONEXT
+
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, #0x1000
+    bic r0, r0, #0x5
+    mcr 15, 0, r0, c1, c0, 0 // disable caches and protection unit
+
+    mov r1, #0
+1:
+    mov r0, #0
+2:
+    orr r2, r1, r0
+    mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
+    add r0, r0, #0x10
+    cmp r0, #0x40
+    bne 2b
+    add r1, r1, #0x4000000
+    cmp r1, #0x0
+    bne 1b
+    nop
+    nop
+    mov r0, #0
+    mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
+    mcr 15, 0, r0, c7, c5, 0 // flush icache
+    mcr 15, 0, r0, c7, c6, 0 // flush dcache
+
+    mov r0, #0x3f
+    mcr 15, 0, r0, c6, c0, 1 // CS0: 4GB at offset 0 - everything
+    mcr 15, 0, r0, c6, c0, 0 // DS0: 4GB at offset 0 - everything
+#ifdef IPOD_NANO2G
+    mov r0, #0x31 // FIXME: calculate that from MEMORYSIZE
+#else
+    mov r0, #0x2f // FIXME: calculate that from MEMORYSIZE
+#endif
+    mcr 15, 0, r0, c6, c1, 1 // CS1: SRAM/SDRAM mirror
+    mcr 15, 0, r0, c6, c1, 0 // DS1: SRAM/SDRAM mirror
+    add r0, r0, #0x08000000
+    mcr 15, 0, r0, c6, c2, 1 // CS2: SDRAM
+    mcr 15, 0, r0, c6, c2, 0 // DS2: SDRAM
+    ldr r0, =0x22000023
+    mcr 15, 0, r0, c6, c3, 1 // CS3: SRAM
+    mcr 15, 0, r0, c6, c3, 0 // DS3: SRAM
+    ldr r0, =0x24000027
+    mcr 15, 0, r0, c6, c4, 1 // CS4: NOR flash
+    mcr 15, 0, r0, c6, c4, 0 // DS4: NOR flash
+    mov r0, #0
+    mcr 15, 0, r0, c6, c5, 1 // CS5: unused
+    mcr 15, 0, r0, c6, c5, 0 // DS5: unused
+    mcr 15, 0, r0, c6, c6, 1 // CS6: unused
+    mcr 15, 0, r0, c6, c6, 0 // DS6: unused
+    mcr 15, 0, r0, c6, c7, 1 // CS7: unused
+    mcr 15, 0, r0, c6, c7, 0 // DS7: unused
+    mov r0, #0x1e
+    mcr 15, 0, r0, c2, c0, 1 // CS1-4: cacheable
+    mcr 15, 0, r0, c2, c0, 0 // DS1-4: cacheable
+    mcr 15, 0, r0, c3, c0, 0 // DS1-4: write cacheable
+    ldr r0, =0x000003ff
+    mcr 15, 0, r0, c5, c0, 1 // CS0-4: full access
+    mcr 15, 0, r0, c5, c0, 0 // DS0-4: full access
+
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, #0x5
+    orr r0, r0, #0x1000
+    mcr 15, 0, r0, c1, c0, 0 // re-enable protection unit and caches
+
+    ldr r1, =0x38200000
+    ldr r0, =0x006A49A5 // default: settings from Apple FW (96 MHz HCLK)
+    str r0, [r1, #0x10] // MIUSDPARA
+
+#else
+
+    ldr r1, =0x3c500000
+    mov r0, #0  // 0x0
+    str r0, [r1, #40] // enable clock for all peripherals
+    mov r0, #0  // 0x0
+    str r0, [r1, #44] // do not enter any power saving mode
+
+#if defined(MEIZU_M6SP) || defined(MEIZU_M3)
+    /* setup SDRAM for Meizu M6SP */
+    ldr r1, =0x38200000
+    // configure SDR drive strength and pad settings
+    mov r0, #SDR_DSS_SEL_B
+    str r0, [r1, #0x4C] // MIU_DSS_SEL_B
+    mov r0, #SDR_DSS_SEL_O
+    str r0, [r1, #0x50] // MIU_DSS_SEL_O
+    mov r0, #SDR_DSS_SEL_C
+    str r0, [r1, #0x54] // MIU_DSS_SEL_C
+    mov r0, #2
+    str r0, [r1, #0x60] // SSTL2_PAD_ON
+    // select SDR mode
+    ldr r0, [r1, #0x40]
+    mov r2, #0xFFFDFFFF
+    and r0, r0, r2
+    orr r0, r0, #1
+    str r0, [r1, #0x40] // MIUORG
+    // set controller configuration
+    mov r0, #SDR_CONFIG
+    str r0, [r1]        // MIUCON
+    // set SDRAM timing
+    ldr r0, =SDR_TIMING
+    str r0, [r1, #0x10] // MIUSDPARA
+    // set refresh rate
+    mov r0, #0x1080
+    str r0, [r1, #0x08] // MIUAREF
+    // initialise SDRAM 
+    mov r0, #0x003
+    str r0, [r1, #0x04] // MIUCOM = nop
+    ldr r0, =0x203
+    str r0, [r1, #0x04] // MIUCOM = precharge all banks
+    nop
+    nop
+    nop
+    ldr r0, =0x303
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    str r0, [r1, #0x04] // MIUCOM = auto-refresh
+    nop
+    nop
+    nop
+    nop
+    // set mode register
+    mov r0, #SDR_MRS
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
+    ldr r0, =SDR_EMRS
+    str r0, [r1, #0x0C] // MIUMRS
+    ldr r0, =0x103
+    str r0, [r1, #0x04] // MIUCOM = mode register set
+#endif /* MEIZU_M6SP */
+
+    mov r1, #0x1
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // disable protection unit
+
+    mov r1, #0x4
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // dcache disable
+
+    mov r1, #0x1000
+    mrc 15, 0, r0, c1, c0, 0
+    bic r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // icache disable
+
+    mov r1, #0
+1:
+    mov r0, #0
+2:
+    orr r2, r1, r0
+    mcr 15, 0, r2, c7, c14, 2 // clean and flush dcache single entry
+    add r0, r0, #0x10
+    cmp r0, #0x40
+    bne 2b
+    add r1, r1, #0x4000000
+    cmp r1, #0x0
+    bne 1b
+    nop
+    nop
+    mov r0, #0
+    mcr 15, 0, r0, c7, c10, 4 // clean and flush whole dcache
+
+    mov r0, #0
+    mcr 15, 0, r0, c7, c5, 0 // flush icache
+    
+    mov r0, #0
+    mcr 15, 0, r0, c7, c6, 0 // flush dcache
+
+    mov r0, #0x3f
+    mcr 15, 0, r0, c6, c0, 1
+    mov r0, #0x2f
+    mcr 15, 0, r0, c6, c1, 1
+    ldr r0, =0x08000031
+    mcr 15, 0, r0, c6, c2, 1
+    ldr r0, =0x22000023
+    mcr 15, 0, r0, c6, c3, 1
+    ldr r0, =0x24000027
+    mcr 15, 0, r0, c6, c4, 1
+    mov r0, #0x3f
+    mcr 15, 0, r0, c6, c0, 0
+    mov r0, #0x2f
+    mcr 15, 0, r0, c6, c1, 0
+    ldr r0, =0x08000031
+    mcr 15, 0, r0, c6, c2, 0
+    ldr r0, =0x22000023
+    mcr 15, 0, r0, c6, c3, 0
+    ldr r0, =0x24000029
+    mcr 15, 0, r0, c6, c4, 0
+    mov r0, #0x1e
+    mcr 15, 0, r0, c2, c0, 1
+    mov r0, #0x1e
+    mcr 15, 0, r0, c2, c0, 0
+    mov r0, #0x1e
+    mcr 15, 0, r0, c3, c0, 0
+    ldr r0, =0x0000ffff
+    mcr 15, 0, r0, c5, c0, 1
+    ldr r0, =0x0000ffff
+    mcr 15, 0, r0, c5, c0, 0 // set up protection and caching
+
+    mov r1, #0x4
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // dcache enable
+
+    mov r1, #0x1000
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // icache enable
+
+    mov r1, #0x1
+    mrc 15, 0, r0, c1, c0, 0
+    orr r0, r0, r1
+    mcr 15, 0, r0, c1, c0, 0 // enable protection unit
+#endif
+
+#if CONFIG_CPU==S5L8700 || !defined(BOOTLOADER)
+    /* Copy interrupt vectors to iram */
+    ldr     r2, =_intvectstart
+    ldr     r3, =_intvectend
+    ldr     r4, =_intvectcopy
+1:
+    cmp     r3, r2
+    ldrhi   r1, [r4], #4
+    strhi   r1, [r2], #4
+    bhi     1b
+#endif
+
+    /* Initialise bss section to zero */
+    ldr     r2, =_edata
+    ldr     r3, =_end
+    mov     r4, #0
+1:
+    cmp     r3, r2
+    strhi   r4, [r2], #4
+    bhi     1b
+
+#if CONFIG_CPU==S5L8700 && defined(BOOTLOADER)
+    /* Copy icode and data to ram */
+    ldr     r2, =_datastart
+    ldr     r3, =_dataend
+    ldr     r4, =_datacopy
+1:
+    cmp     r3, r2
+    ldrhi   r1, [r4], #4
+    strhi   r1, [r2], #4
+    bhi     1b
+#endif
+
+#ifndef BOOTLOADER
+    /* Copy icode and data to ram */
+    ldr     r2, =_iramstart
+    ldr     r3, =_iramend
+    ldr     r4, =_iramcopy
+1:
+    cmp     r3, r2
+    ldrhi   r1, [r4], #4
+    strhi   r1, [r2], #4
+    bhi     1b
+    
+    /* Initialise ibss section to zero */
+    ldr     r2, =_iedata
+    ldr     r3, =_iend
+    mov     r4, #0
+1:
+    cmp     r3, r2
+    strhi   r4, [r2], #4
+    bhi     1b
+#endif
+
+    /* Set up some stack and munge it with 0xdeadbeef */
+    ldr     sp, =stackend
+    ldr     r2, =stackbegin
+    ldr     r3, =0xdeadbeef
+1:
+    cmp     sp, r2
+    strhi   r3, [r2], #4
+    bhi     1b
+
+    /* Set up stack for IRQ mode */ 
+    msr     cpsr_c, #0xd2
+    ldr     sp, =_irqstackend
+
+    /* Set up stack for FIQ mode */ 
+    msr     cpsr_c, #0xd1
+    ldr     sp, =_fiqstackend
+
+    /* Let abort and undefined modes use IRQ stack */
+    msr     cpsr_c, #0xd7
+    ldr     sp, =_irqstackend
+    msr     cpsr_c, #0xdb
+    ldr     sp, =_irqstackend
+
+    /* Switch back to supervisor mode */
+    msr     cpsr_c, #0xd3
+
+// if we did not switch remap on, device
+// would crash when MENU is pressed,
+// as that button is connected to BOOT_MODE pin
+#if CONFIG_CPU==S5L8700
+    ldr r1, =0x38200000
+    ldr r0, [r1]
+    mvn r2, #0x10000
+    and r0, r0, r2
+    mov r2, #0x1
+    orr r0, r0, r2
+    str r0, [r1] // remap iram to address 0x0
+#endif
+
+    bl      main
+
+    .text
+/*    .global UIE*/
+
+/* All illegal exceptions call into UIE with exception address as first
+ * parameter. This is calculated differently depending on which exception
+ * we're in. Second parameter is exception number, used for a string lookup
+ * in UIE. */
+undef_instr_handler:
+    sub    r0, lr, #4
+    mov    r1, #0
+    b      UIE
+
+/* We run supervisor mode most of the time, and should never see a software
+ * exception being thrown. Perhaps make it illegal and call UIE? */
+software_int_handler:
+reserved_handler:
+    movs   pc, lr
+
+prefetch_abort_handler:
+    sub    r0, lr, #4
+    mov    r1, #1
+    b      UIE
+
+data_abort_handler:
+    sub    r0, lr, #8 
+    mov    r1, #2
+    b      UIE
Index: firmware/target/arm/s5l8702/i2c-s5l8702.c
===================================================================
--- firmware/target/arm/s5l8702/i2c-s5l8702.c	(revision 0)
+++ firmware/target/arm/s5l8702/i2c-s5l8702.c	(revision 0)
@@ -0,0 +1,186 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: i2c-s5l8700.c 28589 2010-11-14 15:19:30Z theseven $
+ *
+ * Copyright (C) 2009 by Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+#include "system.h"
+#include "kernel.h"
+#include "i2c-s5l8702.h"
+
+/*  Driver for the s5l8700 built-in I2C controller in master mode
+    
+    Both the i2c_read and i2c_write function take the following arguments:
+    * slave, the address of the i2c slave device to read from / write to
+    * address, optional sub-address in the i2c slave (unused if -1)
+    * len, number of bytes to be transfered
+    * data, pointer to data to be transfered
+    A return value < 0 indicates an error.
+    
+    Note:
+    * blocks the calling thread for the entire duraton of the i2c transfer but
+      uses wakeup_wait/wakeup_signal to allow other threads to run.
+    * ACK from slave is not checked, so functions never return an error
+*/
+
+static struct mutex i2c_mtx[2];
+
+void i2c_init(void)
+{
+    mutex_init(&i2c_mtx[0]);
+    mutex_init(&i2c_mtx[1]);
+
+    /* initial config */
+    IICADD(0) = 0;
+    IICADD(1) = 0;
+    IICCON(0) = (1 << 7) | /* ACK_GEN */
+             (0 << 6) | /* CLKSEL = PCLK/16 */
+             (1 << 5) | /* INT_EN */
+             (1 << 4) | /* IRQ clear */
+             (3 << 0);  /* CK_REG */
+    IICCON(1) = (1 << 7) | /* ACK_GEN */
+             (0 << 6) | /* CLKSEL = PCLK/16 */
+             (1 << 5) | /* INT_EN */
+             (1 << 4) | /* IRQ clear */
+             (3 << 0);  /* CK_REG */
+
+    /* serial output on */
+    IICSTAT(0) = (1 << 4);
+    IICSTAT(1) = (1 << 4);
+}
+
+int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
+{
+    mutex_lock(&i2c_mtx[bus]);
+    long timeout = current_tick + HZ / 50;
+
+    /* START */
+    IICDS(bus) = slave & ~1;
+    IICSTAT(bus) = 0xF0;
+    IICCON(bus) = 0xB3;
+    while ((IICCON(bus) & 0x10) == 0)
+        if (TIME_AFTER(current_tick, timeout))
+        {
+            mutex_unlock(&i2c_mtx[bus]);
+            return 1;
+        }
+
+    
+    if (address >= 0) {
+        /* write address */
+        IICDS(bus) = address;
+        IICCON(bus) = 0xB3;
+        while ((IICCON(bus) & 0x10) == 0)
+            if (TIME_AFTER(current_tick, timeout))
+            {
+                mutex_unlock(&i2c_mtx[bus]);
+                return 2;
+            }
+    }
+    
+    /* write data */
+    while (len--) {
+        IICDS(bus) = *data++;
+        IICCON(bus) = 0xB3;
+        while ((IICCON(bus) & 0x10) == 0)
+            if (TIME_AFTER(current_tick, timeout))
+            {
+                mutex_unlock(&i2c_mtx[bus]);
+                return 4;
+            }
+    }
+
+    /* STOP */
+    IICSTAT(bus) = 0xD0;
+    IICCON(bus) = 0xB3;
+    while ((IICSTAT(bus) & (1 << 5)) != 0)
+        if (TIME_AFTER(current_tick, timeout))
+        {
+            mutex_unlock(&i2c_mtx[bus]);
+            return 5;
+        }
+    
+    mutex_unlock(&i2c_mtx[bus]);
+    return 0;
+}
+
+int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *data)
+{
+    mutex_lock(&i2c_mtx[bus]);
+    long timeout = current_tick + HZ / 50;
+
+    if (address >= 0) {
+        /* START */
+        IICDS(bus) = slave & ~1;
+        IICSTAT(bus) = 0xF0;
+        IICCON(bus) = 0xB3;
+        while ((IICCON(bus) & 0x10) == 0)
+            if (TIME_AFTER(current_tick, timeout))
+            {
+                mutex_unlock(&i2c_mtx[bus]);
+                return 1;
+            }
+
+        /* write address */
+        IICDS(bus) = address;
+        IICCON(bus) = 0xB3;
+        while ((IICCON(bus) & 0x10) == 0)
+            if (TIME_AFTER(current_tick, timeout))
+            {
+                mutex_unlock(&i2c_mtx[bus]);
+                return 2;
+            }
+    }
+    
+    /* (repeated) START */
+    IICDS(bus) = slave | 1;
+    IICSTAT(bus) = 0xB0;
+    IICCON(bus) = 0xB3;
+    while ((IICCON(bus) & 0x10) == 0)
+        if (TIME_AFTER(current_tick, timeout))
+        {
+            mutex_unlock(&i2c_mtx[bus]);
+            return 3;
+        }
+    
+    while (len--) {
+        IICCON(bus) = (len == 0) ? 0x33 : 0xB3; /* NAK or ACK */
+        while ((IICCON(bus) & 0x10) == 0)
+            if (TIME_AFTER(current_tick, timeout))
+            {
+                mutex_unlock(&i2c_mtx[bus]);
+                return 4;
+            }
+        *data++ = IICDS(bus);
+    }
+
+    /* STOP */
+    IICSTAT(bus) = 0x90;
+    IICCON(bus) = 0xB3;
+    while ((IICSTAT(bus) & (1 << 5)) != 0)
+        if (TIME_AFTER(current_tick, timeout))
+        {
+            mutex_unlock(&i2c_mtx[bus]);
+            return 5;
+        }
+    
+    mutex_unlock(&i2c_mtx[bus]);
+    return 0;
+}
+
Index: firmware/target/arm/s5l8702/ipod6g/adc-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/adc-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/adc-ipod6g.c	(revision 0)
@@ -0,0 +1,39 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: adc-s5l8700.c 21775 2009-07-11 14:12:02Z bertrik $
+ *
+ * Copyright (C) 2009 by Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+ 
+#include "config.h"
+
+#include "inttypes.h"
+#include "s5l8702.h"
+#include "adc.h"
+#include "adc-target.h"
+#include "pmu-target.h"
+#include "kernel.h"
+
+unsigned short adc_read(int channel)
+{
+    return pmu_read_adc(channel);
+}
+
+void adc_init(void)
+{
+}
+
Index: firmware/target/arm/s5l8702/ipod6g/adc-target.h
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/adc-target.h	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/adc-target.h	(revision 0)
@@ -0,0 +1,33 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: adc-target.h 21734 2009-07-09 20:17:47Z bertrik $
+ *
+ * Copyright (C) 2006 by Barry Wardell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _ADC_TARGET_H_
+#define _ADC_TARGET_H_
+
+#define NUM_ADC_CHANNELS 4
+
+#define ADC_UNKNOWN_0   0
+#define ADC_UNKNOWN_1   1
+#define ADC_BATTERY     2
+#define ADC_UNKNOWN_3   3
+
+#define ADC_UNREG_POWER ADC_BATTERY /* For compatibility */
+
+#endif
Index: firmware/target/arm/s5l8702/ipod6g/backlight-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/backlight-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/backlight-ipod6g.c	(revision 0)
@@ -0,0 +1,67 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: backlight-nano2g.c 28601 2010-11-14 20:39:18Z theseven $
+ *
+ * Copyright (C) 2009 by Dave Chapman
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdbool.h>
+
+#include "config.h"
+#include "kernel.h"
+#include "backlight.h"
+#include "backlight-target.h"
+#include "pmu-target.h"
+
+#ifdef HAVE_LCD_SLEEP
+bool lcd_active(void);
+void lcd_awake(void);
+void lcd_update(void);
+#endif
+
+void _backlight_set_brightness(int brightness)
+{
+    pmu_write(0x28, brightness);
+}
+
+void _backlight_on(void)
+{
+#ifdef HAVE_LCD_SLEEP
+    if (!lcd_active())
+    {
+        lcd_awake();
+        lcd_update();
+        sleep(HZ/8);
+    }
+#endif
+    pmu_write(0x29, 1);
+}
+
+void _backlight_off(void)
+{
+    pmu_write(0x29, 0);
+}
+
+bool _backlight_init(void)
+{
+    pmu_write(0x2a, 6);
+    pmu_write(0x28, 0x20);
+    pmu_write(0x2b, 20);
+
+    _backlight_on();
+
+    return true;
+}
Index: firmware/target/arm/s5l8702/ipod6g/backlight-target.h
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/backlight-target.h	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/backlight-target.h	(revision 0)
@@ -0,0 +1,29 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: backlight-target.h 21478 2009-06-23 18:11:03Z bertrik $
+ *
+ * Copyright (C) 2008 by Marcoen Hirschberg
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef BACKLIGHT_TARGET_H
+#define BACKLIGHT_TARGET_H
+
+bool _backlight_init(void);
+void _backlight_on(void);
+void _backlight_off(void);
+void _backlight_set_brightness(int brightness);
+
+#endif
Index: firmware/target/arm/s5l8702/ipod6g/button-target.h
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/button-target.h	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/button-target.h	(revision 0)
@@ -0,0 +1,78 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: button-target.h 21828 2009-07-12 22:16:51Z dave $
+ *
+ * Copyright (C) 2006 by Barry Wardell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#ifndef _BUTTON_TARGET_H_
+#define _BUTTON_TARGET_H_
+
+#include <stdbool.h>
+#include "config.h"
+
+#define HAS_BUTTON_HOLD
+
+bool button_hold(void);
+void button_init_device(void);
+int button_read_device(void);
+
+void ipod_mini_button_int(void);
+void ipod_3g_button_int(void);
+void ipod_4g_button_int(void);
+
+/* iPod specific button codes */
+
+#define BUTTON_SELECT       0x00000001
+#define BUTTON_MENU         0x00000002
+
+#define BUTTON_LEFT         0x00000004
+#define BUTTON_RIGHT        0x00000008
+#define BUTTON_SCROLL_FWD   0x00000010
+#define BUTTON_SCROLL_BACK  0x00000020
+
+#define BUTTON_PLAY         0x00000040
+
+#define BUTTON_MAIN (BUTTON_SELECT|BUTTON_MENU\
+                |BUTTON_LEFT|BUTTON_RIGHT|BUTTON_SCROLL_FWD\
+                |BUTTON_SCROLL_BACK|BUTTON_PLAY)
+
+    /* Remote control's buttons */
+#ifdef IPOD_ACCESSORY_PROTOCOL
+#define BUTTON_RC_PLAY      0x00100000
+#define BUTTON_RC_STOP      0x00080000
+
+#define BUTTON_RC_LEFT      0x00040000
+#define BUTTON_RC_RIGHT     0x00020000
+#define BUTTON_RC_VOL_UP    0x00010000
+#define BUTTON_RC_VOL_DOWN  0x00008000
+
+#define BUTTON_REMOTE (BUTTON_RC_PLAY|BUTTON_RC_STOP\
+                |BUTTON_RC_LEFT|BUTTON_RC_RIGHT\
+                |BUTTON_RC_VOL_UP|BUTTON_RC_VOL_DOWN)
+#else
+#define BUTTON_REMOTE 0
+#endif
+
+/* This is for later
+#define  BUTTON_SCROLL_TOUCH 0x00000200
+*/
+
+
+#define POWEROFF_BUTTON BUTTON_PLAY
+#define POWEROFF_COUNT 40
+
+#endif /* _BUTTON_TARGET_H_ */
Index: firmware/target/arm/s5l8702/ipod6g/pmu-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/pmu-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/pmu-ipod6g.c	(revision 0)
@@ -0,0 +1,137 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: pmu-nano2g.c 27752 2010-08-08 10:49:32Z bertrik $
+ *
+ * Copyright © 2008 Rafaël Carré
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "kernel.h"
+#include "i2c-s5l8702.h"
+#include "pmu-target.h"
+
+static struct mutex pmu_adc_mutex;
+
+int pmu_read_multiple(int address, int count, unsigned char* buffer)
+{
+    return i2c_read(0, 0xe6, address, count, buffer);
+}
+
+int pmu_write_multiple(int address, int count, unsigned char* buffer)
+{
+    return i2c_write(0, 0xe6, address, count, buffer);
+}
+
+unsigned char pmu_read(int address)
+{
+    unsigned char tmp;
+
+    pmu_read_multiple(address, 1, &tmp);
+
+    return tmp;
+}
+
+int pmu_write(int address, unsigned char val)
+{
+    return pmu_write_multiple(address, 1, &val);
+}
+
+void pmu_init(void)
+{
+    mutex_init(&pmu_adc_mutex);
+}
+
+int pmu_read_adc(unsigned int adc)
+{
+    int data = 0;
+    mutex_lock(&pmu_adc_mutex);
+    pmu_write(0x54, 5 | (adc << 4));
+    while ((data & 0x80) == 0)
+    {
+        yield();
+        data = pmu_read(0x57);
+    }
+    int value = (pmu_read(0x55) << 2) | (data & 3);
+    mutex_unlock(&pmu_adc_mutex);
+    return value;
+}
+
+/* millivolts */
+int pmu_read_battery_voltage(void)
+{
+    return pmu_read_adc(0) * 6;
+}
+
+/* milliamps */
+int pmu_read_battery_current(void)
+{
+//    return pmu_read_adc(2);
+}
+
+void pmu_ldo_on_in_standby(unsigned int ldo, int onoff)
+{
+    if (ldo < 4)
+    {
+        unsigned char newval = pmu_read(0x3B) & ~(1 << (2 * ldo));
+        if (onoff) newval |= 1 << (2 * ldo);
+        pmu_write(0x3B, newval);
+    }
+    else if (ldo < 8)
+    {
+        unsigned char newval = pmu_read(0x3C) & ~(1 << (2 * (ldo - 4)));
+        if (onoff) newval |= 1 << (2 * (ldo - 4));
+        pmu_write(0x3C, newval);
+    }
+}
+
+void pmu_ldo_set_voltage(unsigned int ldo, unsigned char voltage)
+{
+    if (ldo > 6) return;
+    pmu_write(0x2d + (ldo << 1), voltage);
+}
+
+void pmu_ldo_power_on(unsigned int ldo)
+{
+    if (ldo > 6) return;
+    pmu_write(0x2e + (ldo << 1), 1);
+}
+
+void pmu_ldo_power_off(unsigned int ldo)
+{
+    if (ldo > 6) return;
+    pmu_write(0x2e + (ldo << 1), 0);
+}
+
+void pmu_set_wake_condition(unsigned char condition)
+{
+    pmu_write(0xd, condition);
+}
+
+void pmu_enter_standby(void)
+{
+    pmu_write(0xc, 1);
+}
+
+void pmu_read_rtc(unsigned char* buffer)
+{
+    pmu_read_multiple(0x59, 7, buffer);
+}
+
+void pmu_write_rtc(unsigned char* buffer)
+{
+    pmu_write_multiple(0x59, 7, buffer);
+}
Index: firmware/target/arm/s5l8702/ipod6g/pmu-target.h
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/pmu-target.h	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/pmu-target.h	(revision 0)
@@ -0,0 +1,44 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: pmu-target.h 24721 2010-02-17 15:54:48Z theseven $
+ *
+ * Copyright © 2009 Michael Sparmann
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#ifndef __PMU_TARGET_H__
+#define __PMU_TARGET_H__
+
+#include "config.h"
+
+unsigned char pmu_read(int address);
+int pmu_write(int address, unsigned char val);
+int pmu_read_multiple(int address, int count, unsigned char* buffer);
+int pmu_write_multiple(int address, int count, unsigned char* buffer);
+int pmu_read_adc(unsigned int adc);
+int pmu_read_battery_voltage(void);
+int pmu_read_battery_current(void);
+void pmu_init(void);
+void pmu_ldo_on_in_standby(unsigned int ldo, int onoff);
+void pmu_ldo_set_voltage(unsigned int ldo, unsigned char voltage);
+void pmu_ldo_power_on(unsigned int ldo);
+void pmu_ldo_power_off(unsigned int ldo);
+void pmu_set_wake_condition(unsigned char condition);
+void pmu_enter_standby(void);
+void pmu_read_rtc(unsigned char* buffer);
+void pmu_write_rtc(unsigned char* buffer);
+
+#endif
Index: firmware/target/arm/s5l8702/ipod6g/power-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/power-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/power-ipod6g.c	(revision 0)
@@ -0,0 +1,61 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: power-nano2g.c 28190 2010-10-01 18:09:10Z Buschel $
+ *
+ * Copyright © 2009 Bertrik Sikken
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include <stdbool.h>
+#include "config.h"
+#include "inttypes.h"
+#include "s5l8702.h"
+#include "power.h"
+#include "panic.h"
+#include "pmu-target.h"
+#include "usb_core.h"   /* for usb_charging_maxcurrent_change */
+
+void power_off(void)
+{
+    pmu_set_wake_condition(0x42); /* USB inserted or EXTON1 */
+    pmu_enter_standby();
+
+    while(1);
+}
+
+void power_init(void)
+{
+}
+
+#if CONFIG_CHARGING
+
+#ifdef HAVE_USB_CHARGING_ENABLE
+void usb_charging_maxcurrent_change(int maxcurrent)
+{
+    bool on = (maxcurrent >= 500);
+    GPIOCMD = 0xb060e | (on ? 1 : 0);
+}
+#endif
+
+unsigned int power_input_status(void)
+{
+    return (PDAT(12) & 8) ? false : true;
+}
+
+bool charging_state(void)
+{
+    return false; //TODO: Figure out
+}
+#endif /* CONFIG_CHARGING */
Index: firmware/target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/powermgmt-ipod6g.c	(revision 0)
@@ -0,0 +1,88 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: powermgmt-nano2g.c 28159 2010-09-24 22:42:06Z Buschel $
+ *
+ * Copyright © 2008 Rafaël Carré
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+
+#include "config.h"
+#include "powermgmt.h"
+#include "pmu-target.h"
+#include "power.h"
+#include "audiohw.h"
+
+const unsigned short battery_level_dangerous[BATTERY_TYPES_COUNT] =
+{
+    3600
+};
+
+const unsigned short battery_level_shutoff[BATTERY_TYPES_COUNT] =
+{
+    3350
+};
+
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging disabled */
+const unsigned short percent_to_volt_discharge[BATTERY_TYPES_COUNT][11] =
+{
+    { 3550, 3783, 3830, 3882, 3911, 3949, 3996, 4067, 4148, 4228, 4310 }
+};
+
+#if CONFIG_CHARGING
+/* voltages (millivolt) of 0%, 10%, ... 100% when charging enabled */
+const unsigned short percent_to_volt_charge[11] =
+{
+    3550, 3783, 3830, 3882, 3911, 3949, 3996, 4067, 4148, 4228, 4310
+};
+#endif /* CONFIG_CHARGING */
+
+/* ADC should read 0x3ff=6.00V */
+#define BATTERY_SCALE_FACTOR 6000
+/* full-scale ADC readout (2^10) in millivolt */
+
+
+/* Returns battery voltage from ADC [millivolts] */
+unsigned int battery_adc_voltage(void)
+{
+    int compensation = (10 * (pmu_read_battery_current() - 7)) / 12;
+    if (charging_state()) return pmu_read_battery_voltage() - compensation;
+    return pmu_read_battery_voltage() + compensation;
+}
+
+
+#ifdef HAVE_ACCESSORY_SUPPLY
+void accessory_supply_set(bool enable)
+{
+    if (enable)
+    {
+        /* Accessory voltage supply on */
+//TODO:        pmu_ldo_power_on(6);
+    }
+    else
+    {
+        /* Accessory voltage supply off */
+//TODO:        pmu_ldo_power_off(6);
+    }
+}
+#endif
+
+#ifdef HAVE_LINEOUT_POWEROFF
+void lineout_set(bool enable)
+{
+    /* Call audio hardware driver implementation */
+//TODO:    audiohw_enable_lineout(enable);
+}
+#endif
Index: firmware/target/arm/s5l8702/ipod6g/rtc-ipod6g.c
===================================================================
--- firmware/target/arm/s5l8702/ipod6g/rtc-ipod6g.c	(revision 0)
+++ firmware/target/arm/s5l8702/ipod6g/rtc-ipod6g.c	(revision 0)
@@ -0,0 +1,72 @@
+/***************************************************************************
+ *             __________               __   ___.
+ *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
+ *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
+ *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
+ *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
+ *                     \/            \/     \/    \/            \/
+ * $Id: rtc-nano2g.c 23114 2009-10-11 18:20:56Z theseven $
+ *
+ * Copyright (C) 2002 by Linus Nielsen Feltzing, Uwe Freese, Laurent Baum
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
+ * KIND, either express or implied.
+ *
+ ****************************************************************************/
+#include "config.h"
+#include "rtc.h"
+#include "kernel.h"
+#include "system.h"
+#include "pmu-target.h"
+
+void rtc_init(void)
+{
+}
+
+int rtc_read_datetime(struct tm *tm)
+{
+    unsigned int i;
+    unsigned char buf[7];
+
+    pmu_read_rtc(buf);
+
+    for (i = 0; i < sizeof(buf); i++)
+        buf[i] = BCD2DEC(buf[i]);
+
+    tm->tm_sec = buf[0];
+    tm->tm_min = buf[1];
+    tm->tm_hour = buf[2];
+    tm->tm_wday = buf[3];
+    tm->tm_mday = buf[4];
+    tm->tm_mon = buf[5] - 1;
+    tm->tm_year = buf[6] + 100;
+
+    return 0;
+}
+
+int rtc_write_datetime(const struct tm *tm)
+{
+    unsigned int i;
+    unsigned char buf[7];
+
+    buf[0] = tm->tm_sec;
+    buf[1] = tm->tm_min;
+    buf[2] = tm->tm_hour;
+    buf[3] = tm->tm_wday;
+    buf[4] = tm->tm_mday;
+    buf[5] = tm->tm_mon + 1;
+    buf[6] = tm->tm_year - 100;
+
+    for (i = 0; i < sizeof(buf); i++)
+         buf[i] = DEC2BCD(buf[i]);
+
+    pmu_write_rtc(buf);
+
+    return 0;
+}
+
Index: tools/configure
===================================================================
--- tools/configure	(revision 28885)
+++ tools/configure	(working copy)
@@ -1068,32 +1068,31 @@
   6) AV300                                       26) Mini 2G
                           ==Toshiba==            27) 1G, 2G
  ==Cowon/iAudio==         40) Gigabeat F/X       28) Nano 2G
- 30) X5/X5V/X5L           41) Gigabeat S
- 31) M5/M5L                                      ==SanDisk==
- 32) 7                    ==Olympus=             50) Sansa e200
- 33) D2                   70) M:Robe 500         51) Sansa e200R
- 34) M3/M3L               71) M:Robe 100         52) Sansa c200
-                                                 53) Sansa m200
- ==Creative==             ==Philips==            54) Sansa c100
- 90) Zen Vision:M 30GB    100) GoGear SA9200     55) Sansa Clip
- 91) Zen Vision:M 60GB    101) GoGear HDD1630/   56) Sansa e200v2
- 92) Zen Vision                HDD1830           57) Sansa m200v4
-                          102) GoGear HDD6330    58) Sansa Fuze
- ==Onda==                                        59) Sansa c200v2
- 120) VX747               ==Meizu==              60) Sansa Clipv2
- 121) VX767               110) M6SL              61) Sansa View
- 122) VX747+              111) M6SP              62) Sansa Clip+
- 123) VX777               112) M3                63) Sansa Fuze v2
- 
-                                                 ==Logik==
- ==Samsung==              ==Tatung==             80) DAX 1GB MP3/DAB
- 140) YH-820              150) Elio TPJ-1022
- 141) YH-920                                     ==Lyre project==
- 142) YH-925              ==Packard Bell==       130) Lyre proto 1
- 143) YP-S3               160) Vibe 500          131) Mini2440
-
- ==MPIO==                                        == Application ==
- 170) HD200                                      200) Application
+ 30) X5/X5V/X5L           41) Gigabeat S         29) Classic/6G
+ 31) M5/M5L
+ 32) 7                    ==Olympus=             ==SanDisk==
+ 33) D2                   70) M:Robe 500         50) Sansa e200
+ 34) M3/M3L               71) M:Robe 100         51) Sansa e200R
+                                                 52) Sansa c200
+ ==Creative==             ==Philips==            53) Sansa m200
+ 90) Zen Vision:M 30GB    100) GoGear SA9200     54) Sansa c100
+ 91) Zen Vision:M 60GB    101) GoGear HDD1630/   55) Sansa Clip
+ 92) Zen Vision                HDD1830           56) Sansa e200v2
+                          102) GoGear HDD6330    57) Sansa m200v4
+ ==Onda==                                        58) Sansa Fuze
+ 120) VX747               ==Meizu==              59) Sansa c200v2
+ 121) VX767               110) M6SL              60) Sansa Clipv2
+ 122) VX747+              111) M6SP              61) Sansa View
+ 123) VX777               112) M3                62) Sansa Clip+
+                                                 63) Sansa Fuze v2
+ ==Samsung==              ==Tatung==
+ 140) YH-820              150) Elio TPJ-1022     ==Logik==
+ 141) YH-920                                     80) DAX 1GB MP3/DAB
+ 142) YH-925              ==Packard Bell==       
+ 143) YP-S3               160) Vibe 500          ==Lyre project==
+                                                 130) Lyre proto 1
+ ==MPIO==                 == Application ==      131) Mini2440
+ 170) HD200               200) Application
  171) HD300
 
 EOF
@@ -1660,6 +1659,29 @@
     t_model="ipodnano2g"
     ;;
 
+   29|ipod6g)
+    target_id=71
+    modelname="ipod6g"
+    target="-DIPOD_6G"
+    memory=64 # always
+    arm926ejscc
+    tool="$rootdir/tools/scramble -add=ip6g"
+    bmp2rb_mono="$rootdir/tools/bmp2rb -f 0"
+    bmp2rb_native="$rootdir/tools/bmp2rb -f 4"
+    output="rockbox.ipod"
+    appextra="recorder:gui:radio"
+    plugins="yes"
+    swcodec="yes"
+    bootoutput="bootloader-$modelname.ipod"
+    # toolset is the tools within the tools directory that we build for
+    # this particular target.
+    toolset=$ipodbitmaptools
+    # architecture, manufacturer and model for the target-tree build
+    t_cpu="arm"
+    t_manufacturer="s5l8702"
+    t_model="ipod6g"
+    ;;
+
    30|iaudiox5)
     target_id=12
     modelname="iaudiox5"
Index: tools/scramble.c
===================================================================
--- tools/scramble.c	(revision 28885)
+++ tools/scramble.c	(working copy)
@@ -125,7 +125,8 @@
            "\t                   tpj2, c200, e200, giga, gigs, m100, m500, d2,\n");
     printf("\t                   9200, 1630, 6330, ldax, m200, c100, clip, e2v2,\n"
            "\t                   m2v4, fuze, c2v2, clv2, y820, y920, y925, x747,\n"
-           "\t                   747p, x777, nn2g, m244, cli+, fuz2, hd20, hd30)\n");
+           "\t                   747p, x777, nn2g, m244, cli+, fuz2, hd20, hd30,\n"
+           "\t                   ip6g)\n");
     printf("\nNo option results in Archos standard player/recorder format.\n");
 
     exit(1);
@@ -332,6 +333,8 @@
             modelnum = 69;
         else if (!strcmp(&argv[1][5], "hd30")) /* MPIO HD300 */
             modelnum = 70;
+        else if (!strcmp(&argv[1][5], "ip6g")) /* iPod Classic/6G */
+            modelnum = 71;
         else {
             fprintf(stderr, "unsupported model: %s\n", &argv[1][5]);
             return 2;