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Index: apps/codecs/libmusepack/synth_filter_arm.S
===================================================================
--- apps/codecs/libmusepack/synth_filter_arm.S  (revision 28428)
+++ apps/codecs/libmusepack/synth_filter_arm.S  (working copy)
@@ -116,35 +116,35 @@
     ldmia r2!, { r3-r6 }    /* load D[01..04] */
     ldr r7 , [r1, #96*4]    /*  1 */
     ldr r10, [r1, #992*4]   /* 15 */
+    ldr r11, [r1, #128*4]   /*  2 */
+    ldr r12, [r1, #896*4]   /* 14 */
     rsb r10, r10, r7        /* V[01] - V[15] */
     smull r8, r9, r10, r3
-    ldr r7 , [r1, #128*4]   /*  2 */
-    ldr r10, [r1, #896*4]   /* 14 */
-    add r10, r10, r7        /* V[02] + V[14] */
-    smlal r8, r9, r10, r4
     ldr r7 , [r1, #224*4]   /*  3 */
     ldr r10, [r1, #864*4]   /* 13 */
+    add r12, r12, r10       /* V[02] + V[14] */
+    smlal r8, r9, r12, r4
+    ldr r11, [r1, #256*4]   /*  4 */
+    ldr r12, [r1, #768*4]   /* 12 */
     rsb r10, r10, r7        /* V[03] - V[13] */
     smlal r8, r9, r10, r5
-    ldr r7 , [r1, #256*4]   /*  4 */
-    ldr r10, [r1, #768*4]   /* 12 */
-    add r10, r10, r7        /* V[04] + V[12] */
-    smlal r8, r9, r10, r6
-    ldmia r2!, { r3-r6 }    /* load D[05..08] */
     ldr r7 , [r1, #352*4]   /*  5 */
     ldr r10, [r1, #736*4]   /* 11 */
+    add r12, r12, r11       /* V[04] + V[12] */
+    smlal r8, r9, r12, r6
+    ldmia r2!, { r3-r6 }    /* load D[05..08] */
+    ldr r11, [r1, #384*4]   /*  6 */
+    ldr r12, [r1, #640*4]   /* 10 */
     rsb r10, r10, r7        /* V[05] - V[11] */
     smlal r8, r9, r10, r3
-    ldr r7 , [r1, #384*4]   /*  6 */
-    ldr r10, [r1, #640*4]   /* 10 */
-    add r10, r10, r7        /* V[06] + V[10] */
-    smlal r8, r9, r10, r4
     ldr r7 , [r1, #480*4]   /*  7 */
     ldr r10, [r1, #608*4]   /*  9 */
+    add r12, r12, r11       /* V[06] + V[10] */
+    smlal r8, r9, r12, r4
+    ldr r11, [r1, #512*4]   /*  8 */
     rsb r10, r10, r7        /* V[07] - V[09] */
     smlal r8, r9, r10, r5
-    ldr r10, [r1, #512*4]   /*  8 */
-    smlal r8, r9, r10, r6
+    smlal r8, r9, r11, r6
     mov r8, r8, lsr #16
     orr r8, r8, r9, lsl #16 /* (lo>>16) || (hi<<16) */
     str r8, [r0], #4        /* store Data */
@@ -152,7 +152,7 @@
     add r2, r2, #7*4        /* D+=7, r2 = D[16] */

     /******************************************
-     * rows 01..15 are symmetrc to rows 31..17
+     * rows 01..15 are symmetric to rows 31..17
      * r8  = lo, r9  = hi of 01..15
      * r1  = V[01..15]
      * r10 = lo, r11 = hi of 31..17
@@ -161,74 +161,78 @@
     mov lr, #15
     add r12, r1, #30*4          /* r12 = V[31] */
 .loop15:
-    ldmia r2!, { r3-r6 }        /* load D[00..03] */
-    ldr r7, [r12, #768*4]       /* 12 */
-    smull r10, r11, r7, r6
-    ldr r7, [r12, #864*4]       /* 13 */
-    smlal r10, r11, r7, r5
+    ldmia r2!, { r3-r4 }        /* load D[00..01] */
     ldr r7, [r12, #896*4]       /* 14 */
+    ldr r5, [r12, #992*4]       /* 15 */
     smlal r10, r11, r7, r4
-    ldr r7, [r12, #992*4]       /* 15 */
-    smlal r10, r11, r7, r3
     ldr r7, [r1]                /*  0 */
+    smlal r10, r11, r5, r3
+    ldr r5, [r1, #96*4]         /*  1 */
     smull r8, r9, r7, r3
-    ldr r7, [r1, #96*4]         /*  1 */
-    smlal r8, r9, r7, r4
+    ldr r7, [r12, #768*4]       /* 12 */
+    smlal r8, r9, r5, r4
+    ldmia r2!, { r3-r4 }        /* load D[02..03] */
+    ldr r5, [r12, #864*4]       /* 13 */
+    smull r10, r11, r7, r4
     ldr r7, [r1, #128*4]        /*  2 */
-    smlal r8, r9, r7, r5
-    ldr r7, [r1, #224*4]        /*  3 */
-    smlal r8, r9, r7, r6
-    ldmia r2!, { r3-r6 }        /* load D[04..07] */
+    smlal r10, r11, r5, r3
+    ldr r5, [r1, #224*4]        /*  3 */
+    smlal r8, r9, r7, r3
     ldr r7, [r1, #256*4]        /*  4 */
+    smlal r8, r9, r5, r4
+    ldmia r2!, { r3-r4 }        /* load D[04..04] */
+    ldr r5, [r1, #352*4]        /*  5 */
     smlal r8, r9, r7, r3
-    ldr r7, [r1, #352*4]        /*  5 */
-    smlal r8, r9, r7, r4
+    ldr r7, [r12, #640*4]       /* 10 */
+    smlal r8, r9, r5, r4
+    ldr r5, [r12, #736*4]       /* 11 */
+    smlal r10, r11, r7, r4
     ldr r7, [r1, #384*4]        /*  6 */
-    smlal r8, r9, r7, r5
-    ldr r7, [r1, #480*4]        /*  7 */
-    smlal r8, r9, r7, r6
+    smlal r10, r11, r5, r3
+    ldmia r2!, { r3-r4 }        /* load D[06..07] */
+    ldr r5, [r1, #480*4]        /*  7 */
+    smlal r8, r9, r7, r3
     ldr r7, [r12, #512*4]       /*  8 */
-    smlal r10, r11, r7, r6
-    ldr r7, [r12, #608*4]       /*  9 */
-    smlal r10, r11, r7, r5
-    ldr r7, [r12, #640*4]       /* 10 */
+    smlal r8, r9, r5, r4
+    ldr r5, [r12, #608*4]       /*  9 */
     smlal r10, r11, r7, r4
-    ldr r7, [r12, #736*4]       /* 11 */
-    smlal r10, r11, r7, r3
-    ldmia r2!, { r3-r6 }        /* load D[08..11] */
-    ldr r7, [r12, #256*4]       /*  4 */
-    smlal r10, r11, r7, r6
-    ldr r7, [r12, #352*4]       /*  5 */
-    smlal r10, r11, r7, r5
     ldr r7, [r12, #384*4]       /*  6 */
+    smlal r10, r11, r5, r3
+    ldmia r2!, { r3-r4 }        /* load D[08..09] */
+    ldr r5, [r12, #480*4]       /*  7 */
     smlal r10, r11, r7, r4
-    ldr r7, [r12, #480*4]       /*  7 */
-    smlal r10, r11, r7, r3
     ldr r7, [r1, #512*4]        /*  8 */
+    smlal r10, r11, r5, r3
+    ldr r5, [r1, #608*4]        /*  9 */
     smlal r8, r9, r7, r3
-    ldr r7, [r1, #608*4]        /*  9 */
-    smlal r8, r9, r7, r4
     ldr r7, [r1, #640*4]        /* 10 */
-    smlal r8, r9, r7, r5
-    ldr r7, [r1, #736*4]        /* 11 */
-    smlal r8, r9, r7, r6
-    ldmia r2!, { r3-r6 }        /* load D[12..15] */
+    smlal r8, r9, r5, r4
+    ldmia r2!, { r3-r4 }        /* load D[10..11] */
+    ldr r5, [r1, #736*4]        /* 11 */
+    smlal r8, r9, r7, r3
+    ldr r7, [r12, #256*4]       /*  4 */
+    smlal r8, r9, r5, r4
+    ldr r5, [r12, #352*4]       /*  5 */
+    smlal r10, r11, r7, r4
     ldr r7, [r1, #768*4]        /* 12 */
+    smlal r10, r11, r5, r3
+    ldmia r2!, { r3-r4 }        /* load D[12..13] */
+    ldr r5, [r1, #864*4]        /* 13 */
     smlal r8, r9, r7, r3
-    ldr r7, [r1, #864*4]        /* 13 */
-    smlal r8, r9, r7, r4
-    ldr r7, [r1, #896*4]        /* 14 */
-    smlal r8, r9, r7, r5
-    ldr r7, [r1, #992*4]        /* 15 */
-    smlal r8, r9, r7, r6
-    ldr r7, [r12]               /*  0 */
-    smlal r10, r11, r7, r6
-    ldr r7, [r12, #96*4]        /*  1 */
-    smlal r10, r11, r7, r5
     ldr r7, [r12, #128*4]       /*  2 */
+    smlal r8, r9, r5, r4
+    ldr r5, [r12, #224*4]       /*  3 */
     smlal r10, r11, r7, r4
-    ldr r7, [r12, #224*4]       /*  3 */
-    smlal r10, r11, r7, r3
+    ldr r7, [r12]               /*  0 */
+    smlal r10, r11, r5, r3
+    ldmia r2!, { r3-r4 }        /* load D[14..15] */
+    ldr r5, [r12, #96*4]        /*  1 */
+    smlal r10, r11, r7, r4
+    ldr r7, [r1, #896*4]        /* 14 */
+    smlal r10, r11, r5, r3
+    ldr r5, [r1, #992*4]        /* 15 */
+    smlal r8, r9, r7, r3
+    smlal r8, r9, r5, r4
     /* store Data[01..15] */
     mov r8, r8, lsr #16
     orr r8, r8, r9, lsl #16     /* (lo>>16) || (hi<<16) */
@@ -253,37 +257,37 @@
     ldmia r2!, { r3-r6 }        /* load D[00..03] */
     ldr r7 , [r1]               /*  0 */
     ldr r10, [r1, #992*4]       /* 15 */
+    ldr r11, [r1, #96*4]        /*  1 */
+    ldr r12, [r1, #896*4]       /* 14 */
     rsb r10, r10, r7            /* V[00] - V[15] */
     smull r8, r9, r10, r3
-    ldr r7 , [r1, #96*4]        /*  1 */
-    ldr r10, [r1, #896*4]       /* 14 */
-    rsb r10, r10, r7            /* V[01] - V[14] */
-    smlal r8, r9, r10, r4
     ldr r7 , [r1, #128*4]       /*  2 */
     ldr r10, [r1, #864*4]       /* 13 */
+    rsb r12, r12, r11           /* V[01] - V[14] */
+    smlal r8, r9, r12, r4
+    ldr r11, [r1, #224*4]       /*  3 */
+    ldr r12, [r1, #768*4]       /* 12 */
     rsb r10, r10, r7            /* V[02] - V[13] */
     smlal r8, r9, r10, r5
-    ldr r7 , [r1, #224*4]       /*  3 */
-    ldr r10, [r1, #768*4]       /* 12 */
-    rsb r10, r10, r7            /* V[03] - V[12] */
-    smlal r8, r9, r10, r6
-    ldmia r2!, { r3-r6 }        /* load D[04..07] */
     ldr r7 , [r1, #256*4]       /*  4 */
     ldr r10, [r1, #736*4]       /* 11 */
+    rsb r12, r12, r11           /* V[03] - V[12] */
+    smlal r8, r9, r12, r6
+    ldmia r2!, { r3-r6 }        /* load D[04..07] */
+    ldr r11, [r1, #352*4]       /*  5 */
+    ldr r12, [r1, #640*4]       /* 10 */
     rsb r10, r10, r7            /* V[04] - V[11] */
     smlal r8, r9, r10, r3
-    ldr r7 , [r1, #352*4]       /*  5 */
-    ldr r10, [r1, #640*4]       /* 10 */
-    rsb r10, r10, r7            /* V[05] - V[10] */
-    smlal r8, r9, r10, r4
     ldr r7 , [r1, #384*4]       /*  6 */
     ldr r10, [r1, #608*4]       /*  9 */
+    rsb r12, r12, r11           /* V[05] - V[10] */
+    smlal r8, r9, r12, r4
+    ldr r11, [r1, #480*4]       /*  7 */
+    ldr r12, [r1, #512*4]       /*  8 */
     rsb r10, r10, r7            /* V[06] - V[09] */
     smlal r8, r9, r10, r5
-    ldr r7 , [r1, #480*4]       /*  7 */
-    ldr r10, [r1, #512*4]       /*  8 */
-    rsb r10, r10, r7            /* V[07] - V[08] */
-    smlal r8, r9, r10, r6
+    rsb r12, r12, r11           /* V[07] - V[08] */
+    smlal r8, r9, r12, r6
     mov r8, r8, lsr #16
     orr r8, r8, r9, lsl #16     /* (lo>>16) || (hi<<16) */
     str r8, [r0], #4            /* store Data */