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Index: firmware/target/arm/s5l8700/boot.lds
===================================================================
--- firmware/target/arm/s5l8700/boot.lds	(revision 28328)
+++ firmware/target/arm/s5l8700/boot.lds	(working copy)
@@ -9,8 +9,13 @@
 OUTPUT_ARCH(arm)
 STARTUP(target/arm/s5l8700/crt0.o)

+#ifdef IPOD_NANO2G
+#define DRAMORIG 0x08000000 + ((MEMORYSIZE - 1) * 0x100000)
+#define DRAMSIZE 0x00100000
+#else
 #define DRAMORIG 0x08000000
 #define DRAMSIZE (MEMORYSIZE * 0x100000)
+#endif

 #define IRAMORIG 0x22000000
 #if CONFIG_CPU==S5L8701
@@ -39,19 +44,25 @@
 #if defined(IPOD_NANO2G) || defined(MEIZU_M6SL)
 #define LOAD_AREA IRAM
 #else
+#define NEEDS_INTVECT_COPYING
 #define LOAD_AREA FLASH
 #endif

 SECTIONS
 {
+#ifdef NEEDS_INTVECT_COPYING
   .intvect : {
     _intvectstart = . ;
     *(.intvect)
     _intvectend = _newstart ;  
   } >IRAM AT> LOAD_AREA
   _intvectcopy = LOADADDR(.intvect) ;
+#endif

   .text : {
+#ifndef NEEDS_INTVECT_COPYING
+    *(.intvect)
+#endif
     *(.init.text)
     *(.text*)
     *(.glue_7*)
@@ -90,12 +101,8 @@
      _fiqstackend = .;
   } > IRAM

-  . = DRAMORIG;
-#ifdef IPOD_NANO2G
-  /* The bss section is too large for IRAM - we just move it 12MB into the
-     DRAM */
-  . += (12*1024*1024);
-#endif
+  /* The bss section is too large for IRAM on the Nano 2G, thanks to the FTL.
+     We just move it 31MB into the DRAM */
   .bss (NOLOAD) : {
      _edata = .;
      *(.bss*);
@@ -104,5 +111,9 @@
      *(COMMON);
     . = ALIGN(0x4);
      _end = .;
+#ifdef IPOD_NANO2G
   } > DRAM
+#else
+  } > IRAM
+#endif
 }
Index: firmware/target/arm/s5l8700/crt0.S
===================================================================
--- firmware/target/arm/s5l8700/crt0.S	(revision 28328)
+++ firmware/target/arm/s5l8700/crt0.S	(working copy)
@@ -49,11 +49,7 @@
     .global    _newstart
     /* Exception vectors */
 start:
-#if CONFIG_CPU==S5L8701 && defined(BOOTLOADER)
-    b newstart2
-#else
     b _newstart
-#endif
     ldr pc, =undef_instr_handler
     ldr pc, =software_int_handler
     ldr pc, =prefetch_abort_handler
@@ -66,9 +62,11 @@
 #endif
     .ltorg
 _newstart:
+#if CONFIG_CPU!=S5L8701 || !defined(BOOTLOADER)
     ldr pc, =newstart2 // we do not want to execute from 0x0 as iram will be mapped there
     .section .init.text,"ax",%progbits
 newstart2:
+#endif
     msr     cpsr_c, #0xd3 /* enter supervisor mode, disable IRQ/FIQ */

 #ifdef ROCKBOX_BIG_ENDIAN
@@ -77,7 +75,7 @@
     orr r0, r0, r1
     mcr 15, 0, r0, c1, c0, 0 // set bigendian
 #endif
-             
+
     ldr r1, =0x3c800000 // disable watchdog
     mov r0, #0xa5
     str r0, [r1]